Design And Verification Of Transaction Layer In PCI Express

Due to the network and communication, the processors of Intel and AMD have improved their frequency much. On the other hand, every component needs to exchange data through the bus, so the performance of bus is the performance of whole computer. But as the development of the other component of computer, the PCI bus, most popular bus today, can hardly meet the requirement of these components. The maximum bandwidth of PCI bus is 133MB/s, Maximum Bandwidth = 32bit*33MHz=1066Mb/s=133MB/s.but these finite bandwidth will be used by sound card, network card, video card, USB device and so on. So the bus has been a bottleneck of computer technology. The PCI Express protocol, the third 10 technology, has solved the bandwidth problem from the architecture. So now the problem is how to transport these advantages from theoretical to practical, and the critical problem is the design and implementation of transaction layerThis article can be divided into two parts: theory and implementation. At the theoretical part, beginning with analysis of the specification of PCI Express, introduce the basic concepts of PCI Express, according to the appreciation of author. Then introduce the knowledge of transaction layer, such as: the definition of transaction layer packet (TLP), the way to handle the received TLP, transaction order rules and the most important part: flow control base on credit.The implementation part can also be divided into two parts: design and verification. In the design, with the goal of high performance and low latency, I strictly flow the design requirements of integrated circuit, implement a great pipeline structure. The transaction layer can be separated as transmit part, receive part, error handler and power management. The transmission of TLP in the transmit part is a pinch point, also an innovation of this article, since it first should strictly decide whether a TLP can be transmitted depend on the credit information at that moment, and also should improve the utilization of bandwidth on the condition of follow the transaction ordering rules. In this article, I have used three different type transmit buffer to store the TLPs which are prepared to be transmitted to solve this problem properly. In the verification part, the most critical and difficult thing is the creation of verification environment, because it can influence the result of verification and whether it has ensure the correctness of design. In this verification, according the topology of PCI Express, I have done some modification of the most popular verification environment at this moment, for example: add some modules with self-check function which has improve the efficiency of debug. At the other hand, I have reused the code of reference moduleof Root Complex and Endpoint, since the most function of them is same. At last, in order to ensure the correctness of design, I do simulation and performance analysis with the design which has passed the software simulation on the Xilinx FPGA and got a very excellent result.