Research And Design Of Broadband Frequency Synthesizer Based On Silicon

The frequency synthesizer can provide a variety of operating frequencies for electronic systems and is an integral part of modern RF / analog and digital circuits.For RF transceiver system,the frequency synthesizer is one of the key modules,its integrated design is the development direction of RF integrated circuits.In recent years,the Si Ge Bi CMOS process is popular in the application for RF and high-speed circuits relying on its high performance and low cost advantages and the process is particularly suitable for the realization of PLL frequency synthesizer.Not only that,PLL frequency synthesis method can meet the needs of high-frequency applications,so it has become the mainstream silicon-based frequency synthesis technology.In this paper,the silicon-based broadband frequency synthesizer for X-band is studied,and the integrated design of broadband frequency synthesizer for X-band is completed based on Bi CMOS process and PLL frequency synthesis technology.The research and design of PLL frequency synthesizer in this paper is based on the analysis of PLL as well as the design and optimization of the circuit modules in the loop.Since the internal circuit modules in PLL frequency synthesizer are complex and the property of each circuit module will affect the performance of the overall loop,the linear model of the loop system is established.Relied on this model,the loop noise,stability and transient process are analyzed and the key factors that restrict the performance of PLL are pointed out.Based on those analyses,a number of design and optimization techniques are proposed in this paper.A fully differential PFD based on SCL which can achieve high phase discrimination and function well at high frequency as well as a current steering CP with bias copy loop which can achieve a high switching speed and very low mismatch between the charge and discharge current are adopted in this paper.The combination of those two circuits can effectively overcome the dead zone and reduce the output current noise.As the key module of PLL frequency synthesizer,VCO is the focus of this paper.In order to realize the wide band characteristics,5-bit capacitor arrays are adopted to extend the frequency coverage and more than one analog tuning units are used to expand the available range of the tuning voltage.As phase noise is an important index of frequency synthesizer,corresponding technologies and measures are adopted to optimize the property,such as the tail current source noise filtering technology and the optimization of the size of variable capacitances and MOS switch tubes.High frequency division is a technical difficulty and the divider based on CML which can achieve high operating frequency and reliability is adopted in this paper.Relied on this circuit,the PLL frequency synthesizer can output orthogonal frequency signal.In order to realize the tunability of the output frequency of the PLL frequency synthesizer,a programmable frequency divider is used in this paper.The 8/9 prescaler is still implemented by analog circuit based on CML and the counter part is implemented by digital programming language.To make more in-depth analysis on the stability and dynamic characteristics of the loop,a behavioral model of four-order charge pump PLL frequency synthesizer is built.The simulation and analysis of the model conduct the design of the third-order loop filter.As a result,the design of four-order charge pump PLL frequency synthesizer is finished.According to the simulation results,each circuit module performs well.The VCO's oscillation frequency is covered by 17GHz-25 GHz,the phase noise is-102 d Bc/Hz@1MHz when oscillating at 24.5GHz.In the case of setting the output frequency at 12.5GHz,the digital analog hybrid simulation results show that the loop of the frequency synthesizer is stable and can response rapidly,and the output frequency can be locked in less than 3?s.