Low Power Design And Implementation Of Digital Baseband Of RFID Chip Based On National Standards

With the development of Internet of things(Io T)and large-data technology,automatic identification technology brought about high efficiency and convenience.RFID(Radio Frequency Identification)is a radio frequency information transmission technologywithout contact to achieve automatic identification.RFID system consists of tag,readerand computer or other third-party management system.Tag and reader communicatewith each other,and computer process data for background.The tag consists of tag antenna,RF front-end module,digital baseband and memory.This paper mainly studies the digital baseband part of RFID tag.In the RFID communication system,according to the energy source can be divided into two kinds of active and passive tags.Active tags built in battery and passive tags without internal batteries,so in the research and production to a wide range of concerns,this paper focuses on passive RFID tag chip.More importantly,with the size of the integrated circuit manufacturing process features continue to shrink,deep sub-micron technology has been widely used,power consumption also will be reduced,but in a chip,due to the gates expansion of the integrated circuit,the total circuit power consumption will increase.For passive RFID tag chips,low power consumption is particularly important because of its different ways of acquiring energy.In this paper,the new national-independent standard RFID "radio frequency identification air interface standard" was analyzed and studied,combined with the passive RFID tag chip power consumption,proposed for national-independent standards of low-power RFID tag chip design,the program uses a power management module for the control of other modules to open and shut down,and in the code using the Gray code encoding to reduce the signal flip frequency to reduce power consumption.The architecture design and module division of the digital baseband part of the RFID tag chip based on the national independent standard are realized.The design method of synchronous logic is adopted in the code,which avoids the problem that the asynchronous circuit is difficult to reuse in different technology library.Followed by a gated clock synthesis method,the clock will not need to flip when the gate signal is pulled low,to reduce the gate-level circuit dynamic power consumption.Focusing on the use of two ways to optimize the power consumption of the clock network: the use of clock inverter unit as a clock tree insertion unit,the clock tree is selected by using the clock buffer unit as a clock tree insertion unit or a combination of the two clock Tree,the clock number is the smallest,the number of insertions is the largest,the fastest clock deviation is the smallest,the power optimization is reduced by 7%.In addition,by optimizing the clock transition time to meet the requirement of timing constraint,The transition time of 1000 ps is best suited to the low power requirements of this design.At this point,the completion of the digital back-end design of an important part of the clock network low-power design.The design circuit was followed by a static timing analysis check.Finally,based on the SMIC180 nm process library,the design rules for the generated layout check the DRC,Layout verus schemetic check LVS,and in November 2016 delivery foundry to type out.