H.265/HEVC Intra-Prediction Acceleration Algorithm And Hardware Design

High Efficiency Video Coding(HEVC),namely H.265,the newest video coding standard and a successor of Advanced Video Coding(AVC),markedly improve the compression efficiency compared with other existing video coding standards including AVC.However,it brings a much higher computational complexity,especially in the intra-prediction process.In order to ensure the real-time performance of video coding,it is especially important to design an efficient intra prediction acceleration algorithm to reduce the computational complexity of intra coding.An improved and hardware-friendly gradient based fast mode decision algorithm is proposed in this paper to skip some of the intra-prediction modes and the partition depths for intra prediction.The proposed algorithm can estimate the direction and the complexity of coding-unit texture.Then,the direction of the coding-unit texture can be used to filter out some intra-prediction modes with less possibility to be the optimal intra-prediction mode,and the complexity of the coding-unit texture can determine whether to skip the current partition depth for the intra-prediction process.Experiment shows,compared with the HEVC test model HM16.18,Compared with the HEVC test model HM16.18,the proposed algorithm can significantly reduce about 60.59%of the encoding time on average with 8.52%rate increase and 0.38d B PSNR decrease.In addition to the intra prediction hardware acceleration algorithm,this paper proposes a highly pipelined and parallel H.265/HEVC intra prediction hardware architecture based on this algorithm,supporting all modes and all block sizes.Using TSMC 28nm technology,our hardware design for intra prediction in H.265/HEVC achieves 1.11GHz speed at the cost of 384417.4 um~2 area and supports the1080P@250fps or 4K@60fps real-time encoding with acceptable performance loss.