The Design And Implementation Of A CPLD Whit Embedded Configuration Memory

Complex Programmable Logic Device(CPLD)is one of the most popular Programmable Logic Devices(PLD)in the market.At present,it has vital applications in multiple fields,such as aerospace,automation control,communication and vehicle electronics,etc.It enjoys certain advantages in flexibility,ease of use,cost and development cycle.This topic chooses to design and implement a CPLD chip with 512 macro cells.The chip designed in this paper differs from traditional CPLD which uses EEPROM array to store configuration information.The configuration information is written into the embedded FLASH module for storage and into SRAM scattered across the chip for configuration after it is powered on.The 0 or 1 written into SRAM will be read into the various logic configuration terminals of the chip,including transmission gate control terminal,flip-flop enable pin,combinational logic zero clearing,and so on.This allows controlling the CPLD data transmission path and function by storing different values in the embedded FLASH,thereby enabling CPLD to realize different functions.In summary,as for the chip,autonomous forward design is conducted using the embedded Flash architecture.It is featured by system programming and the data can be loaded into SRAM through the shift register chain after power-on to realize the configuration of CPLD.The chip is capable of providing 600-10000 available gates.512 macro cells contained in the chip form the logic block in groups of 16 macro cells,and thus there is a total of 32 logic blocks.Each logic block contains a programmable and-gate array and or-gate array.Data sharing for each macro cell can be achieved through parallel product term and adjacent macro cells,to enhance the complexity of combinational logic.The macro cell controls its output through a programmable register,either by selecting output to the IO or returning the calculation results to the global routing module for invocation for other macro cells.This chip works with an IO voltage of 3.3V,and as for the core voltage,the dedicated peripheral 3.3V power is converted to 1.8V by LDO.212 user IOs can be provided at maximum,with an ESD design capacity of HBM(Human Body Model)of 2000 V and the function of hot-plugging protection.The encapsulation is in the form of Fineline-BGA256 ceramic packaging and metal cover plate,and IO,core and analog signal grounds are designed separately in terms of the metal layer and tube-shell of the chip,to avoid interfering with each other and connecting together on the board level.This chip works with a temperature range of-55?~125?,the pin to pin delay is controlled within 10 ns at room temperature of 27?,and the maximum operating frequency is 66.7MHz.Parameters such as delay and operating frequency will be guaranteed by critical path building and corresponding post simulation.