Research And Design Of 60GHz RF Attenuator

In recent years,with the rapid development of information technology,the demand for communications transmission rate becomes pressing.60GHz band wireless communication system has many advantages,such as high transmission rate.So far,60GHz band wireless communication system is not mature,a lot of efforts are needed in the 60GHz circuit and system design.On the other hand,driven by the Moore law,the speed of the silicon process is improved a lot,making it possible to realize the 60GHz circuit using silicon process.As an important module in the RF wireless communication and phased-array radar,a lot of efforts is given to the RF attenuator design.Literature survey shows that at present the attenuators are primarily implemented using GaAs process,and CMOS attenuator is still relatively rare.To address the issues above,this thesis presents a 60GHz 6-bit digital step attenuators with low phase variations,basing on 65nm CMOS process.Using Deep N-well process,the phase shift compensation structure is utilized along with the transistor's body-floating technique to achieve small additional phase shift performance and small insertion loss,also improve the attenuation flatness and range.After bit designs are finished,they have to be ordered appropriately to achieve the optimal performance.The bit ordering should be considered in terms of loading effects and power-handling capability.The attenuators employ a correction network that includes a low-pass filter to correct phase/amplitude error.Based on the technology above,the theoretical analysis and simulation verification are carried out.Finally,the 6-bit digital step attenuators in this paper were fabricated with inductive and capacitive correction structures with the high attenuation range of 31.5 dB and the high resolution of 0.5dB.The digital step attenuator with inductive correction exhibits less than 0.5dB/5.2°amplitude/phase RMS errors at 57-66 GHz,layout area is 0.75mm× 0.25mm,the insertion loss at 60 GHz is 8.1dB,the return loss is higher than 6.4dB,P1dB is 16dBm;For attenuator with capacitance compensation structure,in 57-66 GHz band amplitude/phase RMS error is less than 0.7dB/3.1°,layout area is 0.65mm×0.2mm,the insertion loss at 60 GHz respectively is 9.4dB,the return loss is higher than 6.7dB,P1dB is 13dBm.Compared with the GaAs technology,the attenuation and the additional phase shift accuracy of the RF digital step attenuator designed by CMOS technology are higher and the layout area is smaller.