Analysis And Design Of Cmos Integrated Phase-locked Loop Synthesizers In Milimeter-wave RF Front-end

In nowadays,the allure of “being connected” at anytime anywhere and desire for untethered access to information and entertainment “on the go” has set the ever increasing demand for higher data rate. Today limited communication transmission rate can not meet people’s pursuit of large data transfer rate and wideband. The researchers have begun to develop 60 GHz mm-wave communications technology. 60 GHz mm-wave is suit for high data rate, short-range wireless communication system,because of the characteristics of oxygen absorption of 10-15dB/km and wide band.Recently,a lot of institutes in many countries have begun to develop 60 GHz mm-wave communication technology and finished some ICs, used in 60 GHz communication system. Until now, 60 GHz integration technology is under developing, and far from being achieved to realize business application.There are three competing IC techonogies at mm-wave circuits namely : group III-V technique(such as GaAs and InP), Si Ge technology(such as HBT) and silicon technology(such as CMOS). The first two technologies offer fast, high gain and low noise circuits but suffer from poor integration and expensive implementation. CMOS technology is easy to integrate and low production cost and low-power demand. Because of the low fT,the CMOS technology can’t be applied in mm-wave in the early time. As the more developing CMOS technology can offer much higher f T, and can work in nanometer. More and more IC manufacturers have begun to develop mm-wave ICs based on CMOS technique. In this paper we present a PLL design for 60 GHz mm-wave RF front-end. This paper is organised as follows:Section one introduces mm-wave integrated technology,and analyses 60 GHz frequency conversion techniques and synthesizer. What’s more,it analyses the structure, work principle and parameters of PLL. In this design, we have chosen the type –II PLL, a third order system.Section two provides the actual circuit design of every part in PLL. These circuit simulations are based on TSMC CMOS 0.18 um/1.8V model in ADS provided by Agilent. The operating frequency of VCO and prescaler is 11.8~12.3 GHz, and the phase noise is less than-105dBc/Hz@1MHz for VCO. The division ratio is 128. Prescaler is improved from the static frequency divider and the following frequency dividers have chosen static frequency divider( employed CMCL). The rest part in the PLL include PFD(employed D-flip-flop), charge-pump and second-order passive type loop fliter. The actual circuits for every part of PLL have been simulated and optimized in ADS for verifing correctness and improving the performance of circuit design.Section three verify locking time by loop transient simulation,and phase noise contrinbutions for every part by phase noise respone simulation in ADS.