Design Of 6-18GHz CMOS 6-bit Digital Attenuator

With the high-speed developing of 5G communications,phased array technology has become more and more popular.As the key module of phased array radar and communication system,the attenuator is used to adjust the amplitude/power of the received/transmitted signal,and its research and design have become a hot spot of attention by academics in recent years.The mainstream attenuator design schemes are divided into active schemes and passive schemes,each with advantages and disadvantages:Compared with passive attenuators,active structures can achieve higher attenuation accuracy through calibration and reduce the chip area.However,the linearity is slightly worse and additional power consumption is introduced.Compared with the active attenuator,the passive structure has higher linearity and no DC power consumption,but relatively large insertion loss is introduced and takes up a lot of chip area.Therefore,the research and design of the attenuator used in the phased array system has a good engineering background and application value.In this thesis,a 6?18GHz 6bit attenuator is designed based on 40nm CMOS process.The attenuator adopts a two-stage structure of active attenuators cascaded with passive attenuators.The first stage is an active structure.Parallel peaking technology is used to achieve bandwidth expansion,and a cascode switch array is introduced to achieve a 0?16dB attenuation range.The second stage is a passive structure,composed of two bridge T-type attenuation units.Deep N-well suspension technology is used to reduce the insertion loss,and parallel capacitors are used to reduce the additional phase shift to achieve an attenuation range of 16dB.The simulation shows that at the tt process corner and 25?,the attenuation range of the attenuator is 0?31.5dB in the 6?18GHz range.The attenuation accuracy RMS value of the attenuator is 0.052?0.173dB and the additional phase shift RMS value is 0.940?1.973°.Meanwhile,the insertion loss of the attenuator is 4.36-4.41dB with the S11 less than-13.87dB and the S22 less than-13.71dB.Also,the input 1dB compression point of the attenuator is-2.92dBm.The core area of the attenuator is 0.741 mm×0.973 mm,with a total current comsumption of 33.12mA from a 1.2V supply voltage.The attenuator designed in this thesis has good performance and can be used in the 6?18GHz phased array systems.