Research And Design Of A 10 Bit Lower Power SAR ADC

Analog to digital converter is the bridge between analog signal and digital signal.With the rapid development of the technology of digital signal processing,Analog-to-Digital Converters has been used widely.SAR(Successive Approximation Register)ADC is gradually becoming a research hotspot,because it has smaller chip area and can achieve a higher convertion accuracy at a higher sampling rate.Conventionally,successive-approximation register(SAR)analog to digital converters(ADCs)are extensively used in low-power consumption and low-speed(below several MS/s)application.In recent years,with the feature sizes of CMOS devices scaled down,the increasing speed of devices has enabled the SAR ADCs to achieve several tens of MS/s to low GS/s sampling rates with 5-to12-bit resolutions.SAR ADCs have the features of low power and low cost that makes it more appealing for some portable devices or low-power-demand application.This paper presents the design of 10-bit,40-MS/s successive approximation register(SAR)analog-todigital converter(ADC).A new asynchronous control structure is proposed.To reduce the power consumption,the monotonic capacitor switching algorithm is used.To enhance the linearity of ADC,a two-phase non-overlapping clock is used.In order to improve the speed of comparison,redundant MOS transistor is added to the comparator.The prototype was implemented in 0.18?m 1P6 M CMOS process.Under a 1.8-V supply and a 40-MS/s sampling rate,a16.6525 MHz input frequency,the power consumption of SAR ADC is only 0.776 mW,layout area is 0.77736mm~2,SNDR=59.9dB,SFDR=68.5dB.