Study On Design And Test Of Front-end Readout ASIC For Radiation Imaging

The project is supported by the National Instrument Major Project,focusing on the design and test of low-noise front-end readout ASIC.In this paper,a 64 channels low noise front-end readout ASIC for radiation imaging has been designed and tested,which has important theoretical significance and engineering application value for the design of the novel front-end readout chip.The main contributions of this work are follows:1)Study on the theoretical analysis and system design of the low noise readout front-endelectronics.The effects of parameters such as detector capacitance and shaping timeon noise performance are analyzed.2)Study on the test system for readout ASICs,the test system based on FPGA isdeveloped,and several chips are tested.3)Study on the technology of threshold correction for discriminator.The DACarchitecture based on current-steering is designed,including circuit design,layoutdesign,and test.4)Study on test technology of readout chips.A 64 channels readout ASIC is designed.Several technology measures to simplify the testing are proposed,including the datareadout strategy and built-in test circuits.The layout design of the digital circuit iscompleted by the digital automatic synthesis technology and the layout design of thewhole chip is completed by the mixed signal layout technique.The main innovation of this paper includes:1)Proposal for the event-driven data readout strategy of multi-channel front-end readoutchips,which simplifies the data communication of multi-channel front-end readoutchips,and provides new ideas and experimental basis for the design and test oflarge-scale multi-channel front-end readout chip.2)Proposal for the technology of threshold correction for discriminator and built-in testcircuits,which provides new ideas for the test of multi-channel front-end readoutchip.A low-noise 64 channels front-end readout ASIC is designed and fabricated inTSMC 0.35?m technology,chip size is 5000?m × 5000?m.Test results shows,theequivalent noise(ENC)is below 150e-and the energy resolution measured is around 5%full width half maximum(FWHM)at the 59.5keV energy line.This result indicated that it meet the design requirements.A 12-bits DAC based on current-steering is designed and fabricated in TSMC 0.18?m technology,chip size is 490?m × 390?m.Test result shows,the rationality of the structure is verified,greatly reduced the area.The future work is to integrate the DAC,ADC,and JTAG to make the readout system more intelligent.