The Research And FPGA Implementation Of Polar Code Decoding Algorithm

As the only channel code that can be strictly proved reachable to the Shannon limit,polar code had received extensive attention from the communication community since it was proposed.The construction of polar code is based on the channel polarization phenomenon,and the successive cancellation(SC)decoding algorithm with a recursive structure that matches this phenomenon is very suitable for hardware implementation.Other optimized SC series decoding algorithms further improve the decoding performance in short codes.At present,the 5G mobile communication standard had selected it as the coding scheme of the control channel.And in the future,in other fields such as satellite communication and marine communication,polar code also has great development potential.Due to the large delay of the traditional polar code decoding algorithm,this thesis mainly designs and implements a simplified CRC assistant successive cancellation list(S-CASCL)algorithm decoder,aiming to reduce the decoding delay and increase the throughput,while retaining the excellent decoding performance of the traditional decoding algorithm.This thesis mainly completes the following.Firstly,the theoretical basis of polar code is introduced,including the channel polarization phenomenon,as well as several common polar code construction methods.And it also explains how polar codes are encoded.Then several mature polar code decoding algorithms are introduced,including SC,SCL(successive cancellation list)and CASCL(CRC assistant successive cancellation list)algorithms.The CASCL algorithm has quite good decoding performance.The S-CASCL code algorithm proposed in this thesis introduces four kinds of fast nodes(Rate-0,Rate-1,Rep,SPC).During decoding,part of decoding bits that meet the requirements of fast node construction are combined and decoded together,in order to reduce the decoding delay.The performance and latency of several algorithms are simulated and analyzed using Matlab,and the results show that compared with CASCL,the S-CASCL algorithm not only reduces the decoding delay,but also hardly increases the bit error rate.Since SC is the basis of S-CASCL algorithm,several common hardware architecture of SC algorithms is introduced.And then the design ideas and specific schemes of the decoder are elaborated module by module in the thesis.The hardware implementation of the S-CASCL algorithm decoder is based on Xilinx’s ZYNQ7000 series mezzanine card.When the decoder is implemented,a debugging platform jointly with Matlab is also built,and the test results show that the designed hardware decoder has the same bit error rate curve as the software simulation.Finally,a small baseband communication system implemented entirely on FPGA mezzanine card is written for bitstream testing,and the decoder functions is correct.The high-performance,low-latency polar code decoder implemented in this thesis can be practically applied to engineering.