Performance Analysis Of Polar Code And FPGA-based Implementation On Semi-parallel SCL Decoding Algorithm

Channel coding has developed for many years since the Shannon theorem was proposed and many classic encoding and decoding algorithms were put forward,such as LDPC code and Turbo code.However,there was no coding method that can approach Shannon limit.Until Turkey professor Ardal Arikan discovered the channel polarization and proposed the polar code,this channel code method was proved can reach the Shannon limit by mathematical deduction.Polarization codes have linear coding complexity and excellent decoding performance.Under the impetus of 5G,polar codes have high practical value.The main research and innovation points are as follows:(1)We studied the basic coding and decoding methods of LDPC and Turbo codes,and compared with polar code and analyzed their advantages and disadvantages.In addition,we study the generation and properties of channel polarization and it's the theoretical basis of polarization code.Without loss of generality,we can apply the conclusions to other common channels like AWGNs in real communication systems.(2)We study the polar code by channel polarization,and introduce generation matrix of polar code.Then,we study three decoding algorithms: SC decoding algorithm,SCL decoding algorithm and CA-SCL decoding algorithm.Channel selection is an important component of polar code.So,we discuss classical selection methods and propose a new selection method under AWGN channel.First,we transform it to BSC channel,then select channel using Bhattacharyya parameter of BSC channel.(3)Considering the complexity of hardware implementation,we study the minimum-sum algorithm of decoding.It greatly simplifies the complexity of hardware implementation.And then we simulate this algorithm with different quantization width,finally we made a decision with 8 bits LLR and 12 bits path metric.(4)We analyzed several classic SC hardware decoding structures.After comparing their advantages and disadvantages,we decided to use a semi parallel structure to implement the decoding algorithm in FPGA.It can greatly simplify the complexity and has higher system throughput.After a hardware simulation under 150 MHz clock frequency,we draw the conclusion that the throughput of the decoder can be up to 25.6Mbps and the hardware utilization is only 7%.