10Gbps Low Power Adaptive Equalizer Research And Design In 40nm

With the development of the integrated circuit technology,the storage medium interfaces,Ethernet,fiber-optic communication and audio processing of high speed serial interface,the data transmission rate increased rapidly.But due to the heart of high speed serial interface is the analog bandwidth of transmission lines.With the increase of transmission data rate and distance,analog bandwidth of the transmission line is more and more small,which arouse the signal attenuation increasesed.The attenuation signal when arrive at the receiver with severe inter-symbol interference,and even eye diagram has been closed.In order to make the receiver to receive the correct data,the receiver must be adopt some equilibrium technique to eliminate inter-symbol interference,make up the loss in the transmission signal,recover and extract the correct signal from the severe degradation signal.Based on the 40 nm CMOS process,research and design a 10 Gbps low-power adaptive equalizer,which use the combination architecture of analog equalizer and loop-unrolled decision feedback equalizer,sign-based zero-forcing adaptive algorithm,and auto-zeroing technology to compensate offset,makes the receiver equalizer under the condition of meet the requirements to consume lower power.This article mainly includes the following:(1)Analysis signal integrity,digital signal of time and frequency domain characteristics and non-ideal characteristics of transmission line,hereby study the fundamental cause of inter-symbol interference and the characteristics of the equalizer to eliminate inter-symbol interference.(2)Research equalizer's structure and common usage adaptive algorithms,and analysis the performance and power consumption of various equalizer's structure,as well as the common usage adaptive algorithms applicable equalizer's structure,and analysis each type of adaptive algorithm's advantages and disadvantages.Based on this analysis to find the minimum power consumption of adaptive equalizer structure and algorithms,which meet the performance.(3)Through analyze the theory of various modules and modeling Verilog-A for the key modules to determine the concrete realization form of the various modules and the key parameters setting.Analog equalizer adopt the combination structure of continuous time linear equalizer and variable gain amplifier,which can reduce the complexity of design;Decision feedback equalizer adopts new type of loop-unrolled architecture,which can reduce the timing requirements and power consumption;Offset compensation module by make automatic-zero's the mismatch detection work on the equalizer's power-on stage,reduces the power consumption.Through analysis the transmission lines,determine the sequence of detect inter-symbol interference in sign-based zero-forcing algorithm.Through simulation,amplitude detection module can realize 0~450mVpp amplitude detection;Offset compensation module can compensats ? 30 mV mismatch;The whole adaptive equalizer can properly equilibrium for 10 Gbps data at transmission line 0 ~ 23.3dB attenuation,and the power consumption is 32.34 mW.