Research And Design Of A6.25gb/s Analog Adaptive Equalizer In0.18μm CMOS Technology

With the demand for I/O throughput of the transmission increasing, the data rate based on theconventional copper media has reached muti-Gb/s. But the limited bandwidth of copper mediachannel causes the severe high-frequency loss of the signal and results in Inter-symbol Interference(ISI) and Jitter, which deteriorate the signal integrity and limit the signal’s transmission distance anddata rate. In order to transmit data at a higher data rate in copper channel, the equalizer which cancompensate for frequency loss, has been widely used in communication systems.In this dissertation, based on research and analysis of the existing analog equalizationtechniques, a novel6.25Gb/s analog adaptive equalizer has been designed in standard0.18μmCMOS technology. The equalizer mainly consists of an equalizing filter and an adaptive controlloop. The equalizing filter uses a novel improved active negative feedback structure including twovaractors adjusting high-frequency boosting compensation to make the filter’s bandwidth wider andthe range of high-frequency compensation greater. A single loop is used in the adaptive control loop,including slicer, high-pass filter, rectifier and the error amplifier. The slicer is designed in activenegative feedback structure, so as the equalizing filter, and can generate reference signal, fromwhich the adaptive loop can determine whether the circuit is in equalization state. By comparing thehigh frequency energy of the signal after the equalizing filter and the slicer, the adaptive loopgenerates different control voltages adjusting the equalizing filter’s high-frequency compensation,so that equalizing filter achieves the best compensate for the different channels adaptively.With different process corners, simulation results show that the proposed equalizer hashigh-frequency boosting at4GHz, and is able to compensate16~25dB@3.125GHz. Meanwhile, inorder to assess and verify the proposed equalizer’s performance in real channel, the cascade systemis simulated in the typical FR4backplane channels with the length of20”,32” and40”. Simulationresults show the output swing up to270mVpp. The typical values of the peak-peak jitter are0.23UI@5Gb/s and0.26UI@6.25Gb/s. The chip occupies an area of0.62×0.34mm2, of which thecore circuit occupies0.41×0.148mm2, and the total power dissipation is66.6mW with1.8V powersupply. Compared to other designs, this equalizer achieves wider bandwidth, more high-frequencycompensation and smaller chip area.