Study And Design Of 6.25Gb/s Adaptive Decision Feedback Equalizer In 0.18μm CMOS Technology

With increasing data rates, the inter-symbol interference arising from the non-ideal characteristics of channels such as high-frequency loss, reflection, crosstalk and noise, is the key factor that affects the further improvement of data rates. Compared to developing new materials, connectors and improving packaging technology, the enhancement of the I/O circuits’ability to compensate for signal distortion on the basis of low-cost connection is more cost-effective. In addition, since the channel characteristics are unknown or time-varying, adaptive equalization has become a research emphasis.Based on TSMC 0.18μm CMOS process, a 6.25Gb/s adaptive decision feedback equalizer (ADFE) has been designed and implemented in this paper. The Sign-Sign Least Mean Square (S-S LMS) adaptive algorithm is realized by digital and analog two ways. In the DFE circuits,2-tap half-rate structure is employed to reach a compromise of speed, power consumption and equalization performance. The digital adaptive module operates at 781.25MHz, in which a prediction structure is used to reduce the stringent requirement of timing. Meanwhile, a 5-bit current-steering DAC is used to update the tap coefficient, which adopts 2-3 segmented architecture in order to take full advantage of two decoding methods to reduce the circuit size and power consumption. The analog adaptive module works at 1.5625GHz, in which error detection is realized by a sense amplifier with dual differential inputs, and the coefficient is updated by a Gilbert multiplexer and an analog integrator. This structure simplifies the design of the adaptive circuits, while reducing its chip area and improving the work rate.The digital ADFE has been tapped and tested. Its overall area is 0.6×0.55mm2 including I/O pads. Measurement results show that this equalizer can work at the data rate of 6.25Gb/s with horizontal eye opening of outputs larger than 0.8UI. The adaptive module can track the changes of channels, and adapt to signals of different rates or backplane channels of different lengths. The layout design and post-simulation of the analog ADFE has also completed. The post-simulation results show that the equalization effect with the adaptive module on is superior to that of the adaptive module is closed. Both the circuits’rate and adaptive performance have met the design requirements. Under 1.8V power supply, the power consumption of the two ADFE is 45.9mV and 41.4m W, respectively. The studies in this paper has application valve in the design and implementation of high-speed adaptive DFE.