Design And Implementation Of Digital Receiver And Frequency Domain Equalizer Based On FPGA

In recent years,with the rapid development of microelectronics,signal processing technology,etc.,they are widely applied in wireless communication.Software Radio has become the main trend of the future communication technology for development and application.Software Radio emphasizes the use of the simplest open-ended hardware as a common platform,as to achieve a variety of radio function with a reconfigurable,updatable application.So two main issues have to be dealt with,one is how to receive the useful signals in complex electromagnetic environments,and the other one is how to detect the useful information by digital receiver.The flexibility of the process mentioned above is greatly improved by the use of Software Radio.Based on Software Radio architecture,the digital receiver for the actual system performance is designed and realized by FPGA in this thesis.The receiver is mainly composed of digital down-conversion and demodulator.The demodulator receives the signal from the AD,completes the digital down-conversion and performs the matched filtering,the coarse synchronization,the symbol timing synchronization,the carrier synchronization,the frame synchronization and the channel decoding,then the data are sent into the data terminal and are outputted through the optical port.Then,a poly-phase filtered channelized receiver is designed for the reception of any 3KHz bandwidth signal in HF communication system as the existing shortwave digital receiver can not deal with.The receiver can complete the detection of the full HF spectrum and can greatly reduce the difficulty of the receiver and resource consumption.At the same time,according to the phenomenon of multipath fading in the channel of the actual HF communication system,frequency domain equalization is needed to compensate for signal distortion.But the core of frequency domain equalization is FFT/IFFT operation.Therefore,a FFT/IFFT coprocessor is designed and realized,which can be configured based on Hybrid Radix.The coprocessor can achieve FFT/IFFT for any points combined with Radix-2,Radix-3,and Radix-5,and it can also complete configurable processing of the channel information and signal data and can greatly improves the flexibility and practicality of the processing.Finally,the digital receiver and the frequency domain equalizer is tested on the FPGA platform.The test results show that the system is stable and the requirements of system are met.