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Study On Digital Conversion And Adaptive Equalization Technologies In The Intermediate Frequency Digital Receiver

Posted on:2007-09-05Degree:MasterType:Thesis
Country:ChinaCandidate:Y WangFull Text:PDF
GTID:2178360185974427Subject:Circuits and Systems
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Software radio (RS) has being gotten more and more attention in wireless communications field in recent years. Its hardware platform is constructed by using general programmable devices or digital signal processors and its various functions are defined by software. One of the main characteristics of ideal SR is that the ADC and DAC are placed to the antenna as near as possible. Sampling directly at radio frequency in a microwave receiver is impossible up to now because of the limit of today's devices. But the scheme of digitizing at intermediate frequency is feasible and can greatly improve the facility and reliability of the system compared with the conventional digital receiver. This dissertation has deeply studied some key technologies of the intermediate frequency digital receiver based on SR and implemented a hardware platform based on FPGA. The major work done in the dissertation is listed as following:(1) The digitizing architecture of SR receiver was analyzed and summarized. Taking the development level of today's devices into account, this dissertation chose the digitizing architecture sampling at intermediate frequency as the digitizing architecture of the receiver and FPGA as the way of hardware implementing.(2) Digital down-converter (DDC) is one of the key technologies of SR. At the same time, DDC is the most difficult part to be implemented in the receiver. In the intermediate frequency digital receiver, the rate of sampled data flow is very high, so the computing load of DDC is the largest in it. The data width and computing precision of DDC have a direct effect on the performance of the receiver. According to multirate signal processing theory, the CIC filter and half band filter which are used to decimate or interpolate samples were studied for the implementation of the DDC of multi-level decimation architecture. Moreover, the NCO has been optimized, which greatly decreases the scale of the ROM with only a little increase of algorithm complexity.(3) In order to resolve the problem of inter-symbol interference (ISI) because of limited bandwidth of the channel in wireless digital communications, the common adaptive equalizer architectures and interrelated algorithms were deeply studied. The conventional decision feedback equalizer (DFE) was modified by means of error feedback filter. The results of simulation showed that the error feedback DFE is more effective than the conventional DFE especially in the channels with severe ISI without...
Keywords/Search Tags:intermediate frequency digital receiver, digital down-converter, decimation, interpolation, adaptive equalization, error feedback DFE
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