Research And Design Of High Performance Continuous Time Sigma Delta Modulator

With the increasing scale of integrated circuits,the trend of digitizing original analog circuits in very-large-scale integrated circuits is becoming increasingly apparent.Therefore,how to effectively convert analog signals into digital at high speed has become a very significant issue.After decades of development,Nyquist ADCs can achieve GHz-level conversion rates in speed,but it is not easy to achieve higher accuracy in accuracy.Relatively speaking,sigma-delta ADC has great advantages in implementing high-precision converters.The ?? ADC is made up of a ?? modulator and a digital decimation filter.The modulator uses oversampling and noise shaping to improve the signal-to-noise ratio of the modulator.The digital decimation filter section uses a digital method to filter out the high-frequency noise components of the modulator very efficiently and implements ADC down-sampling output.?? ADC can usually be divided into discrete time(DT)?? ADC and continuous time(CT)?? ADC.In contrast,CT?? ADC can achieve higher bandwidth,and due to the inherent anti-aliasing structure,CT?? ADC will occupy a place in the field of high-precision ADCs in the future.So how to design a high precision CT?? ADC becomes very important.This thesis innovatively proposes two types of continuous-time sigma-delta modulators with different structures: single-loop third-order continuous-time sigma-delta modulator and continuous-time MASH2-1-1 cascaded modulator structure.In a single-loop continuous-time sigma-delta modulator,the modulator uses a CRFB structure with a local resonance factor to optimize the position of the modulator's noise transfer function at zero to improve the modulator's signal-to-noise ratio.In response to continuous time sensitivity to clock jitter,this design uses the SCR DAC feedback structure to reduce the impact of clock jitter.In this thesis,the design method of continuous-time sigma-delta modulator is introduced in detail,and the main non-ideal factors in the structure of the modulator are analyzed.The single-loop structure design index is achieved through the simulink behavior-level model and actual circuit simulation.Using the tsmc0.18 process achieves a modulator-to-noise ratio of 79.1dB@OSR=40,which is equivalent to an effective number of digits of 12.8bits.The power consumption of the modulator system is only 1.32 m W.This cascaded modulator adopts a fully-feedforward continuous time MASH2-1-1 structure.The modulators at all levels use CIFF structure to reduce the output range of the integrator,which facilitates the design of the cascade structure.The final simulink behavior-level model simulation results in an ultra-high 164 dB signal to noise ratio.