Design Of High-speed Radiation-tolerant VCSEL Driver Chip

With the rapid development of the society, the optical fiber communication occupies the main position of the communication market because of its advantages such as long transmission distance, large capacity, low power consumption, anti-interference and anti-radiation. How to take the advantages of optical fiber communication and apply it to radiation environment such as aerospace, high energy physics experiments has become an important direction of optical fiber transmission development. The most important thing is whether the light emitting chip as a photoelectric conversion module can meet the requirements of high speed, low power consumption and anti-radiation.Under this background, this thesis uses the SOI technology which has anti-radiation characteristics to design the laser driver chip of the optical fiber communication system.Based on the 0.13 m SOI CMOS technology, the author designed a drive chip of Vertical Cavity Emitting Laser (VCSEL), which is driven by AC coupling mode. The main work is follows: Using multistage cascade amplifier combined with active inductor shunt peaking technique to extended bandwidth, it avoids the process of angular deviation, and reduces the chip area. Design of digital circuit for adjustable bias current and modulation current solves the problem of individual differences in laser, which lay the foundations for the industrial application. Optimizing the design of layout to reduce parasitic and improve the transmission rate of the driver chip.Firstly, the thesis introduces the development of optical fiber communication, the structure and working principle of VCSEL and its driver. On this basis, this paper detailed describe the design method of active inductor shunt peaking circuit as well as auxiliary circuit which contain DAC, bandgap, output buffer. Then according to the coupling mode, introduces the design of simulation circuit and give the simulation results.At the end of this paper, we discuss the matching and parasitic effect of high speed layout design and give the post-simulation results.The simulation of the driving chip shows that this design has good performance when it works at the rate of 5Gbp/s, and the total power consumption is less than 65mW,the chip area is about 1.1 ?mX1.1?m.