Design And Simulation Of Single-Channel Ultra-High-Speed CMOS VCSEL Driver

Modern semiconductor industry is still developing stably following Moore’s Law. However, the increase in performance of inter-chip interconnection is relatively behind with the sharp growth in chip performance. Inter-chip optical interconnection, which uses an optical wave guide instead of metal line, has attracted considerable attention as a promising solution to this problem.The main object of this subject is a single-channel ultra-high-speed VCSEL driver, which convert the electrical signal into an optical signal, providing a suitable current to drive VCSEL lasers work.A VCSEL driver using asymmetric emphasis technique and0.13μm RFCMOS process is designed and simulated for5Gb/s optical-interconnection systems in the paper. Asymmetric emphasis can ensure the rapid transformation VCSEL output waveforms and suppress oscillations.The proposed circuit is simulated using Cadence Spectre, the power consumption of the core circuit is12.8mW. Within the working scope up to5Gb/s, rise time and fall time are no more than86ps,24%smaller than the traditional ones. Eye diagram opens wider than the traditional driver by50%. The design and simulation results are better than the current domestic VCSEL drivers.