Research And SEB Hardening Of Power UMOSFET Device

With the enhancement of people's environmental awareness,high power efficiency and energy conservation are applied into everywhere of human life. As the most popular power device in the applications, there is an increased demand for lower power consumption of the MOSFET. In addition,due to the vast development in Aerospace Science,a huge number of MOSFETs are also used in the environment of space radiation. However, the high-energy particles in space present an imminent threat to the reliability of electronic devices, which increases the requirement for higher radiation resistance of the devices. UMOSFET is developed based on VDMOSFET. It has rather fast progress in the research because of its lower on-resistance and higher integration ability.In this dissertation, the research was focused on three low power consumption designs of UMOSFETs without compromising the breakdown voltage. Each of them has great SEB performance. All designs were simulated and verified by Silvaco TCAD, which are discussed as following:1. Power split-gate resurf stepped oxide UMOSFET with dual channels (DC SG-RSO UMOS).The specific on-resistance of this device is reduced by inserting a P- well and a P+ well in drift region which conducting two inversion channels when the device is under forward conduction. Meanwhile, the P- well and P+ well provide an effective discharge channel to holes, which improves the SEB performance. As shown by the simulation results, without compromising breakdown voltage, the specific on-resistance of DC SG-RSO UMOS is lower than conventional SG-RSO UMOS by 27.4%, and gate-drain charges are lower by 46.3%.The FOM is reduced by 61.0%. The burnout threshold of the DC SG-RSO UMOS is raised to 96.6% of the breakdown voltage.2. Power split-gate resurf stepped oxide UMOSFET with p-pillar (SGP-RSO UMOS).The device is three-dimensional. There is a p-pillar inserted in drift region, thus accelerating the horizontal depletion and increasing doping density of drift region. In the meantime,the burnout threshold is enhanced since hole current is piped away by the p-pillar.The simulation results show that SGP-RSO UMOS has 54.4% and 38.1% lower specific on-resistance under the approximate breakdown voltage, in comparing with ordinary SJ-UMOS and SG-RSO UMOS. To battle the SEB, SGP-RSO UMOS was optimized by extended P+ region and added buffer layer. Therefore, the burnout threshold of the device is raised to 83.1% of the breakdown voltage, and the safe operating area is improved by 1.6 times compared with SJ-UMOS and UMOS SG-RSO with the same buffer layer Furthermore,the effect of cryogenic temperature on SEB was also studied.3. Power oxide bypassed UMOSFET with a Schottky rectifier (sOB UMOS).sOB UMOS is formed up by integrating Schottky diode into OB UMOS cell. It improves the reverse recovery characteristics effectively. Meanwhile, when Schottky diode is on, some of holes will be released from Schottky electrode, thus enhancing the SEB performance. As shown in the simulation results, under the same breakdown voltage, the reverse recovery time of sOB UMOS is 15.1% shorter than the conventional OB UMOS, softness factor is 1.5 times higher, and the peak of reverse recovery current is 73.3% lower. The burnout threshold of the sOB UMOS is raised to 81.4% of the breakdown voltage.Innovation of this paper: three new types of low power UMOSFET are proposed; SEB effect on the three new UMOSFETs is studied.