A Study On The Mechanism Of The SiC/SiO₂ Interface Of SiC MOS Devices

The silicon carbide?SiC?,as one of the third generation wide band gap semiconductors,is an ideal material for the production of energy-efficient and high-voltage power electronic devices owing to its high breakdown voltage and high thermal conductivity.In addition,its ability to growing SiO2 by thermal oxidation as silicon?Si?is the unique advantage over other wide-gap semiconductors,which makes SiC have the possibility to fabricate MOSFET devices.However,the existence of the C element makes the interface state density of SiC/SiO₂ interface is about three times than that of Si.The high interface state density limits the development of 4H-SiC MOSFET devices.The reducing of interface state density can effectively improve the channel mobility.The unveiling of the reaction mechanism at the SiC/SiO₂ interface of 4H-SiC MOS capacitors has become the focus and difficult problem in current research.The main works are summarized as follows:In this paper,the interface problem by high temperature oxide process and post-oxide-annealing process have been researched,the controlling mechanism of the 4H-SiC/SiO₂ interface.1.In this paper,the electrical characteristics,the interface characteristics,the defect types and the composition of defect are studied.It also proposed the solution to reducing SiC/SiO₂ interface state density and studied the origin of interface defects.2.The effects of high temperature on the interfacial properties had been studied.It found that the high oxide temperature may cause the carbon residue at the interface,and the temperature too low will produce oxygen vacancies though the literature investigation and correlation analysis.In order to develop a stable,repeatable high temperature oxide process in dry oxygen,a series of experiments by high temperature oxidation has been investigated.By contrasting interface state density,the interface state density decreased to 2×1012cm-2eV-1 when the oxide temperature was 1450?.3.The paper studied the effects of NO passivation process on SiO₂ gate dielectric.The recent researches show that the N element at the interface will make the interface state density decreased.The paper researched the effects on interface by NO post-oxide-annealing with different temperature and different time.The interface state density decreased to 1.5 ×1012 cm-2 eV-1 when annealing at 1300? for 30min.The quality of the interface improved remarkably compared the annealing time 120min at 1200?,the interface state density is 1.5×1012 cm-2eV-1.In addition,the TDDB gate oxide reliability test results show that the cumulative failure rate of 30min at 1300C0 is 0.1 C/cm-2,the oxide reliability is best.The N element at the interface is more likely to inactivate the interface traps at high temperature.