Double Lattice Oxygen Oxidation Wet Etching And Cleaning Process Before Effect The Performance Of The Thin Oxide Layer Cmos Devices And Its Optimization

The wet cleaning process of semiconductor wafers has become one of the most critical operations in the fabrication of semiconductor devices, especially advanced ULSI silicon circuits. Wet cleaning process include wet etching, wet pre cleaning, wet photoresist stripping, and depending on the detail requirement of process flow in the fabrication of integrated circuits, they exist in the Front-End-Of-Line and Back-End-Of-Line both. In the advanced CMOS circuit technology, dual gate oxidation process is more popular, because of its improvement in the integration of different devices which work with different voltage, such as high voltage for transportation and low voltage for logical calculation. A dual gate oxidation process forms two active areas with different gate oxide thickness through wet etching and2nd oxidation. The thick oxide for the high voltage work area, and the thin for the low. There are total4steps wet processes in the dual gate oxidation flow:the pre cleaning process before the1st and2nd oxidation, wet etching for the low voltage work area oxide, and wet photoresist stripping after wet etching. Being different with the wet process for other purpose, all chemical process in the dual gate oxidation flow will attack the thick gate oxide and silicon at same time, in where a thin oxide will grow. All reaction show significant influence for the property of CMOS devise, especially for the property of gate oxide. In this thesis, all research focus on the wet process between two oxidation steps, the chemicals been used in this flow include Dilute hydrofluoric acid, buffered oxide etchant, sulfuric peroxide mixture, standard clean-1, standard clean-2, etc.Base on experimental and engineering data, this thesis study the optimized solution for maintaining DHF and BOE wet etching process etch rate stability through well control for the concentration reduction, study the optimized solution for maintaining the silicon surface micro roughness status after BOE wet etching process through suitable surfactant introduction and optimized filter lifetime control, study the optimized solution for the chemical oxidation process on silicon surface during the photoresist stripping with SPM through H2O2auto spiking function introduction and well control for the concentration reduction, study the optimized solution to reduce the opportunity for the forming of defect on the silicon surface before the wet pre cleaning process. All data collection prove that these actions are effective.Then, making suitable application with these solutions to improve the character of CMOS device with dual gate oxidation integrated. This thesis study the optimized application for the improvement of the stability for low voltage work area gate oxide’ TXI(electrical thickness), study the optimized application for the improvement of low voltage work area gate oxide’ Qbd, study the optimized application to reduce the opportunity of the forming of pin hole defect, which will induce work function fail for the CMOS device. All these application prove that the wet process is very important for the dual gate oxidation integrated device, and the optimized wet process in dual gate oxidation flow can gain an excellent performance for CMOS device and gate oxide reliability.Further more, in these study, this thesis record the standard analysis flow when CMOS device suffering low yield or WAT fail issue, and the standard evaluation flow when some engineering change exist.