A Process Recipe Improvement For Gate Oxide Of High-voltage MOS Devices

For the high-level geometry of VLSI below 0.25um technique, it is usually used in the formation of STI (Shallow Trench Isolation) etching mode to achieve the purpose of isolated components. Due to the limitation of process ability, the speed of oxidation rate at the corner of STI is different from the one over flat Si substrate, so the thickness and smoothness at the corner of STI of MOS device is more difficult to control. It directly impacts the reliability of the gate oxide layer. Seriously, the TDDB (Time Dependent Dielectric Breakdown) test is hard to get good data.This subject mainly introduces after doing the reliability analysis for EPFLASH (Embedded P-Channel Flash) 0.18um CMOS ( Complementary Metal Oxide Semiconductor) technology product, based on the analysis of the gate oxide VBD (Voltage to Breakdown) reliability uniformity problem, we find out the key chain of the process, then carry out and monitor several tests for a series of purposes. With the data support which is from engineering experiment with the combination of several conditions, we got the conclusion that it is very important to have a control of the STI height after CMP (Chemical Mechanical Planarization) procedure.Finally this subject provides an improved recipe of gate oxide process of high-voltage MOS device. This recipe is mainly about that: With QA in-line SPC (Statistical Process Control) control of STI height after CMP procedure, we can ensure the oxide thickness and smoothness at the STI corner to reach the pre-specified criteria, thus ensure the VBD uniformity of products. At the same time it makes sure the result in TDDB test reaches production criteria. The implementation of the recipe can effectively improve the product yield.