Research On Manufacturing Process And Characteristics Of SiC MOS Capacitor Based On Stacked Gate Oxide

Silicon carbide(SiC)has a wide band gap,high electron mobility and superior thermal conductivity,so it is an extremely attractive material in electronic device applications.As we all know,the insulating SiO₂ layer has excellent dielectric properties,and the quality of the oxide thermally grown on SiC is comparable to the quality of the SiO₂ layer grown on Si,so it is widely used as a gate dielectric material for SiC MOS devices.However,the high defect density in the SiC/SiO₂ structure results in devices with lower inversion layer mobility and poor gate oxide reliability,resulting in unstable threshold voltage and leakage current,which directly affects device performance.Therefore,the improvement of the quality of the SiC/SiO₂ gate dielectric layer is very important for MOS applications.For SiC materials,as the thermal oxidation time increases(the thickness of the oxide layer increases),incomplete overflow of C and incomplete oxidation of Siwill result,resulting in high-density defects.In order to avoid problems caused by long-term high-temperature oxidation,this paper will prepare SiC MOS capacitors based on the PECVD SiO₂/thermally oxidized thin-layer SiO₂/SiC gate oxide structure,and study the influence of the process conditions of the two gate dielectric layers on the device performance.First,low-temperature thermal oxidation produces a thin intermediate dielectric layer,then a thicker SiO₂ layer is obtained by plasma enhanced chemical vapor deposition(PECVD),and then post-deposition annealing is performed,and finally metal electrodes Ni are deposited on the front and back sides respectively to make MOS capacitor.Preliminary experimental results show that the post-deposition annealing process has a greater impact on the performance of the device,and the annealing temperature used in the preliminary experiment is not sufficient to effectively improve the quality of the gate dielectric layer.Furthermore,through the study of annealing conditions after different PECVD SiO₂ deposition(550°C,650°C,750°C,850°C,950°C),it is determined that the annealing temperature after deposition needs at least950°C.At the same time,at a post-deposition annealing temperature of 950°C,we designed the process of the intermediate dielectric layer with different thicknesses.The experimental results show that all samples of the stacked gate structure change from the deep depletion region to the accumulation region.It shows that after annealing at950°C,N₂,1h,the gate dielectric trap charge density decreases.It can be seen from the C-V curve that the addition of the intermediate thin layer can improve the interface quality of the device compared with the directly deposited samples.As the thickness of the intermediate layer increases,the flat-band voltage drift and hysteresis voltage decrease,but the interface state density increases.It shows that the increase of the thickness of the middle thin layer also causes the increase of defects at the interface.The samples of the intermediate layer prepared under high temperature conditions can obtain the lowest interface state density,which may be related to less interface defects caused by high temperature oxidation.Through the I-V(current-voltage)measurement results,it is found that the leakage current is significantly reduced after the introduction of the SiO₂ transition layer,and the breakdown electric field increases.By comparing the effects of thin transition layers of different thicknesses oxidized at 800°C on the capacitor interface characteristics and leakage current characteristics,it is found that as the thickness increases,the breakdown field strength decreases.It shows that there are more C defects or other impurity defects at the interface,which leads to the deterioration of the quality of the intermediate dielectric layer.Through the research work in this paper,it is verified that annealing can improve the electrical performance of SiC MOS devices with stacked gate oxide structure.The influence of the intermediate SiO₂ thickness on the capacitance characteristics of SiC MOS based on PECVD SiO₂/thermally oxidized thin layer SiO₂/SiC is clarified,and the direction of further device performance improvement is predicted based on the existing results.It is of great significance to provide a certain theoretical basis and experimental reference for in-depth research in related fields.