Interfacial Properties And Oxide Trap Capacitance Effect For GaAs MOS Devices With High-k Gate Dielectric

As the scaling down of MOS device dimension,Si-based CMOS technology is approaching the fundamental limit.Due to their higher carrier mobility,III-V compound semiconductors are promising to replace silicon to be used as the channel materials for fabricating MOS devices in the future.Among those materials,GaAs possesses very high electron mobility(?8000 cm2/Vs),thus very suitable to fabricate n-type MOSFETs with ultra-high speed and low power consumption.Also,in order to suppress the increasing gate leakage current induced by the reduced device size,it is inevitable to use the dielectric materials with higher k value to increase the thickness of the gate dielectric.However,directly depositing high-k gate dielectric on the GaAs substrate usually results in a large number of interface traps,which will degrade the device performance.So before the high-k gate dielectric deposition,it is necessary to employ some passivation methods like sulfur passivation,introducing interfacial passivation layer(IPL)or F-plasma treatment,to improve the interfacial properties of the devices.On the other hand,it is usually found that many MOS devices with high-k gate dielectric and GaAs or InGaAs substrate materials exhibit evident capacitance frequency dispersion in the accumulation region.This phenomenon is closely related to the traps in the high-k gate dielectric,so it is very necessary to investigate the effect of the traps in the gate dielectric on the gate capacitance of the MOS devices.Experimentally,the GaAs MOS capacitors are firstly fabricated by depositing LaON,LaGeON or LaSiON as IPL and then ZrON as high-k layer on the S-passivated GaAs wafers.Also,F-plasma treatment is employed to further improve the device performance.From the investigation it is found that LaON and LaGeON IPL can significantly improve the quality of the interface between the ZrON high-k layer and the GaAs substrate,and the better passivation effect can be obtained by LaGeON IPL.As for the samples with LaSiON IPL,the interface quality and electrical properties for the sample with F-plasma treated LaSiON IPL are both better than the sample with F plasma treating the GaAs surface or no F-plasma treatment.Among those MOS devices,the sample with F-plasma treated LaSiON IPL exhibits the best interfacial and electrical properties with low interface-state density(1.08 × 1012 cm-2 eV-1),low platband voltage(0.75 V),large equivalent k value for the gate dielectric(18.3)and small gate leakage current(1.62 × 10-5 A/cm2 @Vfb ± 1 V).Based on the above experimental investigations,further studies have been done by using LaTiON/LaON,ZrTiON/ZrAlON or ZrTiON/ZrLaON gate stack to fabricate the GaAs MOS capacitors,in which LaON,ZrAlON and ZrLaON are used as IPL.From the investigation it is found that incorporating Al or La into ZrON can significantly enhance its passivation effect on the GaAs surface,thus greatly improving the interfacial properties of the devices.Also,as compared to the sample with ZrON as high-k layer,incorporating Ti into the high-k layer(LaTiON or ZrTiON)can effectively increase the gate dielectric equivalent k value(above 25),thus obtaining a smaller capacitance equivalent thickness.The use of the IPLs mentioned above can effectively block the Ti/O atoms in the gate dielectric in-diffusion toward the GaAs substrate,thus protecting the GaAs surface from being oxidized,which can greatly suppress the formation of the defect-related Ga-O,As-O and As-As bonds on the GaAs surface to maintain excellent interfacial properties,and the best passivation effect can be obtained by LaON IPL with the lowest interface-state density of 1.05 × 1012 cm-2 eV-1.Among the gate stacks above,the sample with ZrTiON/ZrLaON gate stack has the best gate-leakage properties and device reliability,and also possesses low interface-state density(1.07 × 1012 cm-2 eV-1)and low platband voltage(0.68 V)Theoretically,based on the Fermi-Dirac statistics and the charging/discharging effects of the traps induced by a small ac signal added into the gate voltage,a theory model about the capacitance effect of the oxide traps in the gate dielectric has been established explain the capacitance frequency dispersion phenomena in the accumulation region for(In)GaAs MOS devices.The proposed model ignores the conductance effect of the oxide traps,thus avoiding the introduction of the imaginary numbers,but doing this will not affect the model accuracy.The capacitance effect of the oxide traps will be introduced into the capacitance system of the MOS devices by two methods:one is approximately thinking that the capacitance effect of the oxide traps is produced at the interface,and another is that thecapacitance effect of the oxide traps is distributed in the gate dielectric,which is consistent with the actual situation.The simulated results indicate that the latter is more accurate,however,the former will also become very accurate when the traps are close enough to the interface.In addition,the effect of the oxide trap location on the gate capacitance of the MOS devices has also been investigated.It is found that only the traps close to the interface can contribute to the gate capacitance.However,among the traps with contribution,the ones close enough to the interface will only lead to the increase of the gate capacitance but have no frequency dispersion contribution,but the ones not close enough to the interface can cause both the increase and the frequency dispersion of the gate capacitance.From the simulation it also can be found that the increase of the k value for the gate dielectric will enhance the gate capacitance frequency dispersion,but in the accumulation region,as the C-V curves reach saturation,the frequency dispersion induced by the oxide traps can be greatly,reduced.