Research And Design Of Readout Circuit For Infrared Focal Plane Arrays

With the development of modern science technology,IR detecting technology is now widely used in Military field,Such as infrared night vision,infrared guidance,high-tech military equipment,etc.In the mean time,it also increasingly comes into people's lives,such as medical,automotive applications,infrared imaging,electronic security and other fields.The quality of the IR imaging systems hinges on two vital points:1)the performance of the Focal Plane Arrays(FPA)as the transducer of the electromagnetic wave and 2)the Readout Integrated Circuit(ROIC)that transforms the pixel data to the processing unit.In this thesis,the readout circuit of infrared focal plane array is studied and designed,and a high dynamic range infrared focal plane array readout circuit is designed successfully.The main contents and achievements of this paper are as follows:1)Readout circuit designed in this paper uses capacitive transimpedance amplifier structure as the pixel interface circuit,and multiple integral capacitors are used to achieve wide dynamic range.In addition,the correlated double sampling circuit is introduced to remove the reset noise and improve the noise performance of the readout circuit.The readout circuit has an area of 25?m×25?m,and the array format is 320×256.2)To achieve high dynamic,this design placed two signal processing chains in each column that are used to process the signal generated from pixel circuit in high gain and low gain mode,which can output two images in one frame time.Through high dynamic synthesis algorithm,we can get a high dynamic range image from two images described above.3)In order to improve the frame rate,the column readout circuit is divided into four blocks,each block uses a common analog output channel.The frame rate of this readout circuit can reach 100 frames per second or more.The readout circuit bias is generated on the chip without off-chip supply.In addition,the bias and the gain of column level readout circuits can be adjusted by on-chip SPI.4)This design uses XFAB 180 nm 1P4M technology,and the overall chip area is 10mm×10mm with 500 mW total power consumption.The whole circuit is designed and simulated by cadence software.