Research And Design Of Read-out Circuit For Uncooled Infrared Focal Plane Arrays

Infrared imaging technique is becoming more and more common, and expected to be usedin many fields, especially in the military fields. Infrared focal plane array (IRFPA) is a keypart of infrared imaging system. Owing to the significance of IRFPA for military stratagem,some developed countries have been attaching great emphasis on the developing andresearching of the IRFPA for a long time, and we need to develop our own IRFPA. IRFPAis mainly made up of two parts: detector and readout-circuit. There are high requirementson its readout-circuit, such as low power consumption, stable detector bias, small pixel sizeand pixel pitch, especially ways of suppressing the background current before theintegration node in the large background current situation to improve the detectingsensitivity and the signal noise ratio, and to reduce the integration time and integrationcapacitor.Aiming at the above problems, this author has read many latest related references, andanalyzed the principle of uncooled IRFPA of various types. After then introduced theadvantages and disadvantages of the several readout-circuit structures which are adoptedextensively. Finally, we select the CTIA as a pixel level circuit. It also uses a correlateddouble sampling (CDS) technique and row selection mode. The circuit composes of pixellevel circuit, buffer isolation, correlated double sampling circuit, differential amplifier, outputbuffer, and addressing circuit. Finally, its degree of linearity is more than99%.The transistors in amplifier of CTIA work in sub-threshold region, which can reducethe power to2μW. The CTIA in this paper not only has the advantages of general CTIAcircuit, but also has simple structure and small area. So it can be used in large area array,and to work under the background in high and low illuminance. In the meanwhile, thecolumn circuit uses correlated double sampling that utilizes noise time correlation methodto eliminate most of the noise. And Addressing circuit reads one line once, and a newlow-power quasi-dynamic shift register is adopted. It has low power dissipation near to zerofor the static power.The author analyzed, simulated, and accomplished designing the correspondingcircuits the circuit in the Cadence IC system with the SMIC18mm process rule. Finally, itsummarizes the work of this paper and gives some ideas on the next step of work.