Reserch On 1280×1024 Uncooled Infrared Focal Plane Array Readout Circuit

With the wide application of uncooled infrared focus plane array in military and civil, one of the main development trends of uncooled infrared focal plane array is high reliability and low cost chip which has the advantages of larger array, smaller pixels and higher integrated level. Uncooled infrared focal plane array includes the infrared focal plane array detectors and readout circuits, as the connecting part of the infrared focal plane array detector and signal processing system, the performance of readout circuit directly influences the property of uncooled infrared focal plane arrays.In this dissertation, we research on readout circuit of uncooled infrared focal plane array with larger array and smaller pixels. A 1280×1024 uncooled infrared focal plane array readout circuit in which the pixel dimensions are 12μm×12μm are proposed.This readout circuit can work normally at high frame frequency which has the function of adjustable master clock frequency and integral time. This design is completed by CSMC 0.5μm process and the schematic design, simulation, layout design, verification are finished by using Cadence EDA tools. The main contents and results of this dissertation are summarized as follows:1. The design requirements of a 1280×1024 infrared focal plane array readout circuit is that the frame frequency is 60 Hz, master clock frequency is 19.66 MHz, NETD is not more than 80 mK, the area of the chip must be less than 19.116mm×20.4mm, and the power consumption of the chip is not more than 300 mW. The main two difficulties of 1280×1024 infrared focal plane array readout circuit are high frame frequency and spatial nonuniformity of large array. Firstly, multiunit read mode is proposed as array scan mode. Secondly, the whole 1280×1024 array is divided into 4 sub 320×1024 arrays with two output ports each. Lastly time division multiplexing is used between rows when the analog channel deal with readout singals.2. The digital module is defined by various logic functions include: the central timing controller, row selection timing controller, row selection controller and mux selection controller. Then we do a detailed circuit design, time series analysis and simulation of each module. The central timing controller generates a series of sequential logic control signal by using shift registers, Coder/Decode method is applied to row selection control, the shift register control method is proposed to mux selection control. According to the main function of the analog circuits and design indexes, we finish the detailed analog circuits design and simulation of Integrator amplifier, buffer, BGR.3. The whole circuit is simulated to evaluate the chip power consumption and confirming the scan mode. The overall arrangement of the readout circuit layout is put foward, clock tree synthesis is adopted and the routs of clock singal have equal length to vrarious registers in layout to assure the same time delay. The design of the digital module layout is discribled. Finally, the whole layout of the readout circuit of uncooled infrared focal plane array pass through the DRC, ERC, LVS verification, and the whole area of the chip is 16.13mm×16.22 mm.