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The Research On Protect Technology Of Soft Error For Digital Integrated Circuit

Posted on:2018-11-21Degree:MasterType:Thesis
Country:ChinaCandidate:R J MaFull Text:PDF
GTID:2348330515493502Subject:Electrical engineering
Abstract/Summary:PDF Full Text Request
With the technology feature size enters nanometer level,soft error induced reliability problem is a major reliability concerns in deep submicron technology.Accompanying with the technology feature size shrinks,a latch is becoming more and more susceptible to soft errors generated by energetic particles.This paper presents a low overhead radiation hardened latch design,which uses C-element to tolerate the SEU(Single Event Upset)and restore the corrupted node.In order to achieve lower-power and high-speed,the proposed latch applies Clock Gate and Power Gate.For the function of tolerating SET(Single Event Transient),the proposed latch needs one more delay element to tolerate SET.The main work of this paper is as follows:Firstly,the development of the integrated circuit and the research status of the domestic and foreign research on the soft error are briefly introduced in this part.Secondly,some basic knowledge of soft error is introduced and single event effect is classified in this chapter.The influence of SEU and SET on the integrated circuit is introduced in detail.Thirdly,some classical latch structures are introduced.In this part,the latches that can tolerate SEU will be introduced before the SET-immune latches.Besides the analysis of the working principle,the advantages and disadvantages are also pointed out.Finally,a low overhead radiation hardened latch design is proposed.In this chapter,the scheme,process and protecting principle of the proposed latch are introduced.Simulation experiment is carried out and relevant data will be obtained.The analysis about the delay,power and performance of the proposed latch is based on the collected data.Through the comparison with other classical latches,we can tell what the advantages of the proposed latch are.The proposed latch applies Clock Gate and Power Gate,which help the proposed latches save 46%delay and 88.9%power comparing to the FERST(feedback redundant SEU/SET-tolerant latch)latch under the same SEU-Immune capability.By the HSPICE simulation experiment,the proposed latch is better than the FERST in many aspects.
Keywords/Search Tags:soft error, SEU, SET, Latch
PDF Full Text Request
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