| Since the founder of information theory Shannon put forward the concept of channel encoding,scholars began to devote themselves to study channel coding to achieve near performance with low complexity,easy implementation.In the last century in 60s,Robert Gallager first proposed LDPC(Low Density Parity Check Codes)code.However,due to the limited computing power,LDPC has not attracted the attention at that time,until 1996,the excellent performance of LDPC code was re-discovered.Over the years,the integration of FPGA and other devices is increasing.Because of the powerful function of FPGA,it has become one of the first choices in hardware design now.Therefore,in this thesis,we use FPGA to design and implement a kind of LDPC code which can take throughput,resource and complexity tradeoff.This thesis first analyzes and compares the error correcting performance and decoding complexity of several LDPC code decoding algorithm.Because their low complexity,the Min-Sum algorithm and EMS algorithm are chosen for implementation of the binary LDPC decoder and no-binary LDPC decoder respectively.Then,we selected suitable structure as the basic structure of parallel decoder implementation.In addition,the decoder can support a variety of flexible code rate and code lengths of LDPC codes,and it is functional of continuous data processing and stop iterative dynamically.After that,this thesis built a functional simulation platform based on Modelsim 6.5C to test and verify the decoder.Then the decoder is synthesized by Xilinx ISE 14.6 with Xilinx XC6VSX315T.The synthesis results show that the decoder in this thesis has higher throughput,lower complexity. |
