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The PC Software’s Design And Realization Of Circuit Test System Based On JTAG Interface

Posted on:2015-03-11Degree:MasterType:Thesis
Country:ChinaCandidate:H QianFull Text:PDF
GTID:2308330473450875Subject:Measuring and Testing Technology and Instruments
Abstract/Summary:PDF Full Text Request
With the continuous development of the large scale integrated circuit technology, the component becomes smaller, and the circuit also becomes more complex. As a result, the traditional test method already can not adapt to this development trend. In order to meet the development, the JTAG(Joint Test Action Group) proposed the boundary scan theory, and formed the IEEE 1149.1 standard in 1990. Abroad, many test equipment providers developed test systems based on boundary scan standard, including the test controller and PC software; at home, the research and application of the standard is still in its infancy. When in testing, PC software is one of the most important, the test vector generation and test response analysis are implemented in the PC software. In this paper, the main research work is the design and implement of the PC software.In this paper, the PC software is developed in VS2010 development platform based on the MFC framework, and conducts the following several aspects of the analysis, design and implementation.Firstly, this paper studies the principle of boundary scan, such as TAP port, TAP controller, instruction and data registers, etc. After that, the paper analyzes three kinds of circuit extension method and the test process. At the same time, it analyzes the format of netlist file and BSDL file, prepared for reading these two files.Then this paper analyzes the demands of PC software. Demand analysis is an important part in software development; it can have the effect of getting twice the result with half the effort to software programming.And then this paper analyzes the specific design and implementation of PC software. In the paper, the PC software are divided into four modules: the test file processing module, test vector generation module, USB communication module and the project management and interface design module. The test file processing module is divided into BSDL file processing and netlist file processing, completes extracting information by reading BSDL file and netlist file; the test vector generation module completes the vector generation of the ICODE instruction, SAMPLE instruction and EXTEST instruction; the USB communication module completes the coding of the USB communication class by using CyAPI provided by Cypress, and realizes the communication with the test controller; the project management and interface design module achieves the project files and friendly operation interface.At last, through joint debugging of the upper computer, hardware controller and the under test circuit board, debugging results show that the PC software developed in this paper, can realize the expected demands, namely the ID code test, dynamically display pin’s state, set the pin’s state and other functions.
Keywords/Search Tags:IEEE 1149.1, Boundary Scan, BSDL, NetList, CyAPI, INI
PDF Full Text Request
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