The Debug System Design And Research In Complex Multicore System

With the deep integration of embedded system and FPGA development technology, the System-on-a-Programmable-Chip (SOPC) based on FPGA has obtained theunprecedented vigorous development. According to design requirements, the software and hardware of FPGA development platform has flexible choices, programmbalbe characteristics and personalization are favored by developers. The configurable Microblaze softcore processor and reusable IP can realize microprocessor technology,SOPC technology and soft-hard collaborative design by the bus and peripheral hardware,reducing design difficulties, shortening system development time, improving resource reuse rate and having become the mainstream. But, facing the design complexity and performance improvement of the complex multicore system, as well as the more difficult software and hardware debug tasks,the traditional testing methods and debug measures can hardly ensure the function correctness of chip design under the limited condition. The high verification cost makes it difficult to successfully complete chip design with the limited manpower and material resources. To improve the debug quality, the effective and efficient debug technique is key. The emergence of SOPC technology can change the traditional debug methods, reduce the software-hardware design time and cost, and improve the debug efficiency of multicore system.Aiming at deep research of debug system in the complex multicore system, the design and implementation of practical debug system can realize information and data tracing,monitoring,modulation and control. The main content and work of this thesis is as follows:Firstly, this thesis gives the detail research and analysis about the current multicore debug technology and the architecture characteristics of the heterogeneous multicore programmable system based on Network-on-Chip (NoC), and completes the software code self-refresh design. According to the characteristic of the target system, the user can implement a configurable, programmable, scalable, protable and practical debug system,which can realize to trace and monitor the key data information, control target system,schedule relative tasks,restore the working process, reduce the debug time,and accelerate the process of the chip design.Secondly, deep analysis and research of the debug system include debug architecture based on mechanism and characteristic of target system, debug commands and data transmission mechanism, four kinds of debug mode, debug interface and relative software-hardware module. The SOPC technology and soft-hard coordination design can realize a highly efficient, practicable and portable debug system, and accomplish the debug command design and the corresponding debug process.Finally, completing the detail software and hardware collaborative design of the debug system based on EDK tool, and integrating debug system into the multicore system, it can complete collaborative testing of input/output device in the Virtex-6 XC6VLX760 FPGA.In the test task sets, the thesis chooses classical large FFT convolution to complete algorithm analysis, mapping and function verification base on FPGA board.Without affecting the normal task operation of the target system, the result shows that debug system can complete the real-time monitoring, system control and task tracing by the friendly obeservation interface. The experiment proves that debug project in multicore system has certain feasibility. The debug system has two new characteristics, namely SOPC technology and collaborative design method of software and hardware. It can meet multicore debug requirements as well as practical application value.