Study On The Method Of SOPC HW-SW Co-design

SOPC technology is first raised by US Altera corporation in 2000, as the result of the development of CAD EDA and VLSI design technology. Broadly speaking, SOPC (System on a Programmable Chip) belongs to SoC (System on a Chip), is a kind of chip design methods on system level. In a narrow sense, SoC technology designs chips using ASIC as the physical carrier, while SOPC uses FPGA. Some disadvantages exsit in the traditional design method, such as the HW-SW developing process dissevers and lacks of communication. Hardware-Software co-design is put forward as to solve these shortcomings. HW-SW co-design is a new trend along with the complication of electronic system. SoC and SOPC are representatives of this trend. SOPC offered a more convenient and more reliable realization manner for the design of system chip. However, the SOPC design is not mature both in theory and practice.This thesis emphasizes on the study of SOPC HW-SW co-design method. Several modeling means of SOPC system are provided. Two HW-SW co-partition algorithm -simulated annealing algorithm and genetic algorithm are compared. Besides, this article analyses the SOPC HW-SW co-design method based on the Nios II embedded processor. The SOPC target system's architecture is also given. In the field of SOPC design based on Nios II processor, this thesis first combines simulated annealing algorithm with genetic algorithm to partition hardware and software of the SOPC target system. The Nios II developing platform is designed, and the SOPC target system is achieved using this platform. Through comparison, a better design scheme is applied. The target system mainly implemented three functions: blinks 4 LED on the core board according to the streaming lights law; UART terminal prints "Hello, Nios II!" ;draws a heart-shaped dynamic pattern on a 8*8 dot-matrix LED on the base board, and a smiling face static pattern on another 8*8 dot-matrix LED.