Research On EOSVI-CFAR Algorithm And Its Hardware Design And Implementation

CFAR processing in the radar system is designed to guarantee a constant false alarm rate during the detection for targets. The detection performance of different CFAR algorithms varies when the background changes.By studying classical CFAR algorithms, it is found that VI-CFAR presents robust performance in homogeneous environment and control the Pfa well in clutter environment, however it become bad in multiple targets environments. Considering this situation, this paper proposes an enhanced VI-CFAR(EOSVI-CFAR) algorithm which combines VI-CFAR and OS-CFAR and change the methods to select CFAR algorithm more wisely.The simulation results using MATLAB show that EOSVI-CFAR improves the detection performance in the multi-target environment and keeps a high performance in homogeneous and clutter environment meanwhile.Hardware design follows after algorithm simulation. According to the spec, the paper gives a feasible plan for hardware implementation,the core blocks of the plan include cumulative sum block, cumulative multi block, judgment block, control block, threshold block and insert sort block. In order to enhance the max clock frequency of the CFAR processor, a new hardware implementation method is proposed based on the original plan in the lab, the simulation result using ISE Virtex5 shows that the modified circuit is 10% faster than it was before. Also, a reusable structure is applied in sort and cumulative block which effectively decreases the chip area.At the stage of verification, MATLAB and Modelsim is used simultaneously, the simulation results obtained from Matlab is compare with ones from Modelsim, the accordant results prove the RTL code is correct. The code is systhsised using SMIC0.18μm in DC®, the area of the netlist is 760106μm2 and the max clock frequency at the worst case reach 215MHz。The latency for the first data needs 31 clock cycle. The Formality® result shows the correctness of design. Finally,with the support of standard cell library, the backend design is realized using ICC®. The final core area after place & route is 1520233μm2 and the power consumption is 67.8m W.