Static Control And Application Study In IC Spin Clean Application

In IC (Integrated Circuit) manufacture, there is outstanding benefit on yield improvement. Wet process is the high ratio process section in IC manufacture flow, it is over 100 step in typical wafer manufacture flow. During wet process, control defect is the high priority task since it is strongly relative the wafer yield. Electrostatic induced defect is hardly to eliminate or remove than other kinds defect, such as surface particle, organic contamination.Electrostatic induced defect has been taken some study on dry etch process, discharge could damage wafer film and metal inter-connection, and increase wafer surface contamination. The most important is that it does not only damage surface pattern, but also impact the dielectric property, finally impact IC device reliability, some TDDB (Time-Dependent Dielectric Breakdown) has been reported. The thesis focus on optimize chamber inside mini-environment and wet process to control electrostatic induced defect. Also discussion on wafer transfer and chuck material impact on electrostatic.Single wafer clean is the wet clean tendency. The thesis analysis wafer surface defect scan and electrostatic distribution map to study the defect root cause in spin clean. Also base equipment and fab automation view look into electrostatic induced defect, attempt to get a system solution to overcome the defect and improve IC manufacture yield. Base on electrostatic source, elimination model and actually case analysis, Figure out a optimization procedure on electrostatic elimination efficacy, and ion system optimization solution; Figure out a solution on controlling high conductivity chemistry arcing risk during process electrostatic wafer; Improvement current wet process sequence to achieve different application custom electrostatic control recipe; Design wafer surface charge close loop control solution, and induce APC(automatically process control) perform in wafer surface charge control.