Copper Interconnect Process Defect Pattern And Its Effect On Ic Yield

This paper will brief introduce copper interconnect technology-the so called Dual-damascene technology.Due to totally different from conventional aluminum interconnect technology,the defect mode of copper interconnect is also different.The impact of yield is also different. And this paper will simply introduce concept of yield.The yield discussed in this paper is wafer yield.That is ratio of good dies completed all process steps divided by gross die per wafer.In wafer process, exponential relation between yield and kill defect can be expressed by formula.In copper interconnect process,the failure modes are only show short,open and void on physical structure of chips.The damage of physical structure can result in open,short,leakage and function failure etc. Anyone of those test items failed,the die will be give FAIL by ATE.ATE can identify which item is failed like parameter,I_DDQ or function.In the foundry or fabless company,yield engineer and product engineer is responsible for yield analysis on test data.This paper will analyze yield modle by 3 approaches:wafer map analysis;memory BIST and bitmap;IDDQ analysis and OBIRCH.Then to further do failure analysis.Finally engineers will find out the correlation between yield failure mode and defect mode.The copper interconnect defect has been investigated widely and deeply.But research the issue of how copper interconnect defect impact yield is rarely been discussed due to professional limited. Especially systematic defect can impact yield significantly.What this paper discussed is know-how critical systematic defects of copper interconnect impact yield from die electrical failure.