Lithography Process Optimization For Eliminating The Surface Static Electricity Of Trench MOS

Among many kinds of power MOSFETs, Trench MOSFET has lower turn-on resistance, small gate-drain charge density, low conduction resistance and switching losses, and faster switching speed. A special trench MOS structure named"product-A"structure, that has increased gate wire area, can further reduce resistance and power consumption, and increase switching speed. However, the conventional process technology can not meet the yield requirement of this novel Trench MOS product A. This work is focused on lithography process improvement for increasing Trench MOS product-A yield. This project analyzes the low yield mechanism of product-A through a series of experiments, especially the impact of lithography develop process parameters. Experimental results show that, within develop process, reducing the time of ultra-pure water rinse can improve yield. The impact of this approach is assessed and the results obtained demonstrate the feasibility of using this technique. In order to assess the effect of this process improvement, it is applied to the actual mass production process. The mass production results show that reducing ultra-pure water rinse time made the yield improve and reach the target value. The results show that this method can eliminate the wafer surface electrostatic charge accumulated within P-well photo process, reduce its impact on P-well implantation uniformity, and eliminate the threshold voltage variation across wafer. In addition, the method can improve the product throughput.