Modeling NBTI Effect And Its Reliability Design Based On 40nm CMOS Technology

With the shrinking of transistor size,the Negative Bias Temperature Instability(NBTI)has become one of the most important factors to affect the reliability of circuit.Based on 40nm CMOS technology,this paper firstly researches the parameters'extraction of NBTI effect,and then describes the model and its parameters using VerilogA to build up an equivalent aging voltage source,the clock skew degradation of clock network is studyed at last.The main works are as follows:1)The parameters of Reaction-Diflfusion(R-D)and Trapping/Detrapping(T/D)models are extracted based on the 40nm CMOS experimental data,and a two-step(Coarse-Fine)parameter extraction method has been proposed.2)Based on the extracted model parameters,an equivalent NBTI aging voltage source described using VerilogA has been built-up.It will be embedded into the PDK library for Hspice and Spectre.The degeneration characteristics of the inverter under NBTI effecting are simulated,and the simulation results show that the proposed method can effectively reflect the time-domain degradation characteristics of digital logics.3)The propagation delay of an inverter has been numerically simulated,and it is exqpressed as a function of threshold voltage,capacitance load,and input transitio.By curve fitting,a degradation model has been built-up.Moreover,an analysis method of clock skew for non-gated clock tree is proposed.The degradation of clock skew of benchmark circuit(ISCAS85-s38417)has been calculated and the results has been compared with Hspice simulation,giving an error of 3.3%.This method can satisfy the requirement of analyzing clock skew degradation.In addition,the clock skew of gated clock tree is simulated and predicted by using the equivalent NBTI aging voltage source,and the clock network is optimized based on the simulation results.The parameter extraction methods,models,and ctock skew analysis enrich the theories of reliability design,and can be the fundenmental and reference for high performance and high reliability integrated circuit design.