Research And FPGA Implementation Of Downlink Synchronization Algorithm In TD-LTE Boardband Trunking System

The traditional narrow-band digital trunking communication system is difficult to meet the users' wide demand for data and video services with the users continue to surge.There is an urgent need to use broadband technology for digital trunking communication system's research and development.LTE,as the 4G mobile communication standard,has a strong industrial strength and outstanding performance in terms of rate,bandwidth and spectral efficiency.The international industry develops broadband trunking communication system vigorously based on LTE technology.There has been basically formed a consensus in China that broadband trunking communication system should be based on TD-LTE.Downlink synchronization process is the most critical and most important step in TD-LTE system,and the system can work correctly only if the downlink synchronization is completed.In this paper,firstly,we study the influence of timing error and frequency offset on the received demodulation signal;Then,we focus on the analysis of the downlink time-frequency synchronization,and build a downlink physical layer simulation link based on MATLAB,verifying the correctness of the algorithm;Finally,we implement the synchronization algorithm based on FPGA,and build a TD-LTE physical layer test link,Testing and verifying the time-frequency synchronization module and the uplink and downlink communication links.The details are as follows :The first chapter introduces the basic procedure of downlink synchronization process and uplink random access,and the influence of timing error and frequency offset on system performance is analyzed,emphasizing the importance of synchronization technology in TD-LTE systems.The second chapter studies the downlink time-frequency synchronization algorithm from two aspects: time synchronization and frequency synchronization,including PSS coarse synchronization procedure,PSS accurate synchronization procedure,SSS detection,integer frequency offset estimation and compensation,fractional frequency offset estimation and compensation,and propose an optimization method to improve the algorithm's performance.Then the algorithm is verified via matlab.The simulation results of the main parameters that characterize the synchronization performance are given and analyzed.It is proving that the algorithm is achievable.In the third chapter,according to the actual system design requirements,we implement the downlink time-frequency synchronization algorithm based on FPGA,and the design scheme of each module is introduced in detail.Under the premise of guaranteeing the performance of the algorithm,the implementation complexity and the resource occupancy rate of the algorithm are reduced,and the Modelsim simulation of the implemented module is given.The simulation results of some key parameters are given and analyzed.It is demonstrating that the FPGA implementation of the functional simulation is correct.In the fourth chapter,the FPGA program is tested on the actual hardware platform,and the corresponding test results are given and analyzed,indicating that FPGA implementation of the algorithm is valid.At the same time,we build the system level test link,testing and verifing the correctness of the system's uplink and downlink.In the fifth chapter,the content and main work of the full thesis are briefly summarized.The shortcomings to be improved and the directions of future effort are pointed out.