Fault-tolerant Routing Of Multi-core Processors And The Granularity Modeling Study

As the growing development of semiconductor technology, multicore and even manycore processors are the general trend of processor design domain, and so interconnect infrastructures are becoming more important. But decreasingly smaller feature size and increasingly higher integration makes it difficult to guarantee correct fabrication with an acceptable yield. And also due to aging effects like electro-migration and time dependent dielectric breakdown of devices during lifecycle, some parts of the chip will fail. To improve the reliability, fault-tolerant interconnect infrastructures are important to provide the required communication for NoCs in spite of failures.The proposed reconfigurable fault-tolerant distributed Routing (RFDR) algorithm, partitions the system into nine regions using the concept of divide-and-conquer. Nine regions tolerate fault patterns located within each region respectively, and they cooperate well to tolerate several fault regions to improve the fault-tolerance capability. The proposed RFDR has excellent scalability with hardware cost keeping constant independent of system size. Also it is completely reconfigurable when new nodes fail. Flexible routing restriction sets can not only promise the deadlock freedom, but also balance the traffic. SystemC based simulations under various synthetic traffic patterns show its better performance compared to Extended-XY routing algorithm. It is implemented in 130nm CMOS process and there is almost no hardware overhead compared to Logic-Based Distributed Routing (LBDR), but the fault-tolerance capacity is enhanced in the proposed RFDR. Hardware cost is reduced 37% compared to Reconfigurable Distributed Scalable Predictable Interconnect Network (R-DSPIN) which only supports single fault node or extended to one region.As to homogeneous multicore processors, due to inherent redundancy to replace the faulty nodes, we further model and quantitatively analyze it. We give a theory model of the homogeneous MPSoC system from as many as available (AMAA) and as many as demand (AMAD) these two aspects, analyzing the yield and average performance to be achieved with various granularities. Meanwhile, we discuss the MTTF feature of different core sizes, then model the system performance taking processing capability and communication latency between cores into consideration, and propose a metric to present a high level view of homogeneous MPSoC system design named 3D space exploring. To the best of our knowledge, this is the first time that combines yield and performance of homogeneous MPSoC, and lifetime reliability of uni-core from granularity point of view, and provides some design rule for high level MPSoC modeling.