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Research On Fault-tolerance Technology Of Fault-Aware And High-Reliability Router In Three-Dimensional Network-on-Chip

Posted on:2015-02-28Degree:MasterType:Thesis
Country:ChinaCandidate:M HeFull Text:PDF
GTID:2308330473957015Subject:Computer technology
Abstract/Summary:PDF Full Text Request
The performance of three-dimensional Network-on-Chip (3D NoC) has been greatly improved by the benefits from the vertical link design and the scalability of Network-on-Chip. It has lower power consumption and greatly improved the system performance. But as the feature size of transistors in Integrated Circuits (IC) is close to atomic scale, the transistors face the reliability problems caused by process instability, electron transfer, dielectric breakdown, hot carrier injection, negative bias temperature instability and cosmic radiation irradiation. The reliability of IC is confronted with great challenge, and easily to cause fault occurred in router of 3D NoC. Therefore, this thesis will make an intensive study of fault-tolerant problems and key technologies of input buffers and switch crossbar. The main ideas are as follows:(1) This thesis describes the development of IC and the research background of the 2D NoC and 3D NoC, and it also introduces the topology, virtual channel technology, the basic structures of the router, and the related fault-tolerant knowledge.(2) To solve the problem of router fault in 3D NoC, this thesis proposes a flexible and configurable high-reliability router architecture, each input channel is connected to two adjacent buffers, By means of modeling, the router architecture selects appropriate input buffer paths to achieve partial buffers sharing on the basis of the specific faults and congestion, This method can not only achieve the goal of fault-tolerance for router faults, but also efficiently solve the congestion problem of the entire network under the heavy network load.(3) Researching and analyzing the VOQ architecture using for reducing network latency, this thesis proposes a fault-tolerant and fault-aware modified VOQ router design by adding a redundant virtual channel (VC) and modifying crossbar architecture. When fault or congestion occurs in one VC, our router can transmit data using the redundant VC; modified crossbar can ensure the data transmission when fault occurs. Our scheme has obvious advantage and ensures the high-reliability and low-latency of the entire network when congestion and faults occur.
Keywords/Search Tags:3D Network-on-Chip, Buffer, Crossbar, Reliability, Fault-tolerance
PDF Full Text Request
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