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Research On Architecture And Mapping Algorithm For Network-on-Chip In Dark Silicon Era

Posted on:2017-02-22Degree:MasterType:Thesis
Country:ChinaCandidate:G FengFull Text:PDF
GTID:2348330509962921Subject:Circuits and Systems
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Recently, integrated circuit design is faced with new problems called dark silicon, which means part of the cores on chip needs to be shut off or operate in short cycles in order to maintain the performance of multi-core system and not exceed the thermal design power. And new challenges have been brought for Network-on-chip( NoC), the communication architecture of multi-core systems-on-chip. The thesis carries out the research on the NoC architecture and mapping algorithm under dark silicon era.Firstly, we propose a new NoC architecture based on distributed manager which takes distributed manager and multi-mode router as key components. According to the requirements of different applications, the distributed manager manages the mapping of application and set the mode of multi-mode router, which could save power consumption effectively. Furthermore, considering the influence of the number and placement of the distributed manager, the paper presents a power-aware placement algorithm based on genetic algorithm. Compared with the common placement, the results show that our optimal placement could save 15.26% communication power consumption and 26.36% network delay.Based on the NoC architecture we proposed, a power-aware dynamic mapping algorithm is proposed, which contains two steps: select mapping region and map tasks. Experiments take several multi-applications to verify the efficiency of the proposed algorithm. Results show that our algorithm could save 20.6% and 24.8% communication power consumption compared with NN and Tree algorithm respectively, and reduce 13% and 16.67% network delay.An irregular region routing algorithm is proposed for the irregular regions formed by different applications.The algorithm takes adjacency state table to route packets in the regular regions, which can avoid closed-mode router and take advantage of the bypass-mode router reducing the communication distances between nodes. Take experiments on multi-mode routers connected NoC architecture, our algorithm can save 20.8% of packet transmission power on average compared with the existing irregular routing algorithm CDOR. Finally, the design of the distributed manager and the multi-mode router in the RTL level is completed, and the power consumption and area of distributed manager and multi-mode router in the proposed NoC architecture are evaluated.
Keywords/Search Tags:Network-on-Chip, dark silicon, mapping algorithm, architecture, router design
PDF Full Text Request
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