Design And Implementation Of Network On Chip Base On Cluster Network

With the advancing of electronic and circuit technology, the number of IP cores integrated in a single chip is increasing. The traditional bus architecture cannot satisfy the communication requirements of these IP cores. Network on Chip (NoC) has emerged as a new technique to provide high performance communication among the IP cores. It overcomes the critical communication problems of IP core so that low latency, low power consumption and high throughput can be obtained.In this thesis, Network-on-Chip and some associated concepts have been overviewed and their advantages and disadvantages are also analyzed. In addition, in order to overcome the limitations of traditional mesh based NoC, a new cluster architecture based on Cmesh is proposed. It includes topology, router architecture, mapping and configuration algorithms, etc. We mainly focus on the designing of8X8router architecture including input/output flow control, input buffer, routing computation, crossbar allocator and crossbar module, etc. This router architecture can be used to construct cluster NoC. Then a hardware emulation platform is developed with Verilog and it is synthesized by Synplify. Finally, the operation frequency and resource utilization are evaluated according to the synthesis reports. The final results indicate that the proposed cluster NoC outperforms the traditional mesh NoC, and the performance is improved dramatically. Based on these work, a cluster NoC mapping algorithm is proposed to achieve low power consumption. Then, a specific design flow of topology mapping algorithm is presented. Moreover, a mapping optimization model with specific objective function is established and it is adapted to cluster architectures. The results demonstrate that the hardware costs and power consumption can be improved compared with the traditional mesh topology.