Design And Evaluation Of Switch Allocation For Networks-on-Chip

As the number of cores on a single chip keeps increasing, the Network-on-chip(No C) technology is becoming more and more important and has become a bottleneck of performance improvement in chip multiprocessors(CMPs). Switch Allocation(SA) is the critical pipeline stage of a router in No Cs, which makes big difference to the performance of routers and even the whole network and has become a hotspot in NOC researching. Traditional SA is designed based on long packets while most of packets in NOCs are short packets, which makes traditional SA is not suitable for NOCs. Therefore, it has become the crux of improving the performance of NOCs to design efficient single-cycle SA strategies based on the characteristic that most of packets in NOCs are short ones. Based on the above problems, this paper will spread the content from the following four aspects:1. We analysis and summary the methods of traditional SA based on the in-depth understanding of current development situations of NOCs and SA. We go into the characteristic of packets transmission in NOCs as well as the challenge it brings to the design of SA. We also analysis and summary the methods of short-packet-aware SA in order to design efficient SA method.2. Based on the analysis of efficient SA methods in NOCs, we propose to apply efficient SA methods in low-latency routers to improve the performance of NOCs. We design and implement short-packet-aware switching, such as TS-Router, in low-latency router. This method lowers the latency of packet transmission and improves the throughput of NOCs.3. We propose a new SA method named Reorder Buffer based on on-line scheduling; this method is designed to solve head-of-line(HOL) blocking in input-queued(IQ) routers. This method reduces the conflicts in SA by scheduling the order of packets buffered in input ports, and as a result improves the matching efficiency of SA. We evaluate the performance of Reorder Buffer using Booksim simulator, and the results show that Reorder Buffer can reduce network latency and improve throughput efficiently; the performance of it is even better than TS-Router.4. In order to reduce the network latency in NOCs, we propose to combine high-radix topology with efficient SA method. We layout Dragonfly in NOC and evaluate the performance of using efficient SA methods such as TS-Router. The results show that high-radix topology can reduce packet latency in NOCs and the performance can be improved more by using efficient SA methods under certain kinds of routing functions.In summary, this thesis aims to ‘optimizing the design of SA in NOCs'. Based on the analysis of the characteristics of NOCs, we design and optimize the SA methods in NOCs, and improve the performance more by combining other advanced technologies in NOCs. Thus, this thesis solves some practical problems in on-chip SA, and has both engineering value and theoretical significance.