Research On Buffer Allocation And Dynamic Routing Algorithm Of Network-on-Chip

As the device feature size is continuously shrinking, System-on-Chip (SoC) development is confronted by severe challenges, such as managing deep submicron effects, scaling communication architectures and bridging the productivity gap. Traditional shared-bus architecture which is inherently non-scalable and power hungry will no longer be able to meet the requirements of SoC implementations.Network-on-Chip (NoC) have emerged as a promising alternative to address the above problems associated with on-chip buses by employing a network for inter-IP communication. In this dissertation, we formulate and address several key research problems in wormhole-switched NoC design, namely, buffer resources allocation, virtual channel allocation, routing algorithm and NoC network performance analysis.Buffers are an integral part of any network router. The traditional uniform assignment of buffering resources leads to excessive use of the silicon area. We propose a buffer allocation algorithm to assess the performance of wormhole switched NoC with finite size buffers. When the total budget of the available buffering space is fixed, the proposed algorithm assigns the buffer depth for each input channel, in different routers across the chip, according to the traffic characteristics of the target application, such that the overall communication performance is maximized.The virtual channel (VC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels uniformly results in a waste of area and significant leakage power. We propose a novel algorithm for customizing the VC resources. The proposed algorithm calculates the bandwidth usage at each router based on the traffic characteristics of the target application, and adds VCs only to the channels with the highest bandwidth usage.In addition, we also investigate the problem of routing for NoC. We propose a novel deadlock-free dynamic routing algorithm for wormhole-switched NoC. The proposed algorithm introduces the concept of multilevel congestion-aware mechanism, which conveys more accurate feedback information about the network congestion status than the DyAD routing algorithm, to choose proper routing algorithm according to the current congestion status.Network performance analysis plays a central role in the NoC design. We use SystemC to design and implement the NoCSim simulator, which is a NoC performance analysis platform. Using this platform, our experimental results show that the proposed algorithms can benefit significantly from the implementation of NoCs in terms of performance improvement and energy/resource efficiency.