Design And Implementation Of Power Balanced Chip Based On AES Algorithm

With the rapid development of the Internet,the degree of informatization of the entire society is getting higher and higher,and information security is paid more and more attention by people.Cryptographic chip,as one of the protectors of information security,is widely used in national defense,commerce,finance and other fields.However,the emergence of Side Channel Attack(SCA)technology poses a serious threat to the cryptographic chip.Power attack is the most effective SCA technology.Faced with the increasingly serious security issues,chip security has become the focus.Dual Rail Pre-charge Logic is an efficient method to resisit power attack because of its balance power.Based on LBDL(LUT Based Differential Logic),this paper designs a power balance chip based on AES(Advanced Encryption Standard)algorithm,which has high practical value and research value.The innovations of this thesis are as follows:For the question of symmetry routing about dual rail signal,This thesis proposed a Dual-rail Signal Parallel method based on blocking the power hole.This method processes the through-holes in the power network after the power network planning is completed,and then sets the routing blockage blocking layers based on the track for each layer of metal,performed clock tree synthesis and route.And then expanded the single rail signals to dual rail signals.And the GDSII data of the balanced dual rail routing will be formed.For the problem that there are too many IO ports for AES power balancing logic and the demands for defferent data input when capturing chip power consumption,peripheral test logic based on JTAG(Joint Test Action Group)interface is designed.It reduced the number of IO and achieve the input control and output observation of the AES module.In addition,according to the problem that the power consumption data of the power balance logic need to be collected separately,the design method of using the dual power supply is proposed.Based on the proposed wiring method and the design method of the peripheral test circuit,a complete AES power balanced chip is designed under the 55 nm process.The chip can control the input and observe the output of AES module,and it can separately collect power consumption of AES algorithm module in different working conditions,which has a high practical value and research value.