Research And Implementation Of SOC Test Scheduling Control Network Based On IEEE Standards

As the SOC integration increases and the size of the process feature continues to decrease,the number of test vectors that can be generated using a testable design for the fault of the chip become larger and therefore the cost of testing is increasing.It is expected that the fault testing cost of the chip will exceed its manufacturing cost in 2020,so it is imperative to reduce the total cost of the chip by reducing the failure test time of the chip without reducing the coverage rate of the fault test.Two methods can be used to solve this problem: one is an efficient data test scheduling control network;the other is a more advanced test methodology.According to the features of the Tessent tool on the development process of the DFT design,this paper uses a top-down design method to design a SOC test scheduling control network based on IEEE standards to meet various circuit fault test requirements to reduce the time of chip fault testing,thereby reducing the cost of fault testing.The SOC test scheduling control network is designed for the following test strategies: digital circuit test adopts full scan test technology,memory test adopts MBSIT test technology,chip boundary test adopts BSCAN test technology,analog circuit test adopts function vector test.The main body of the design adopts the IEEE 1149.7 standard distributed multi-TAPC scanning topology,the SIB control network structure of the IEEE 1687 standard is used to access embedded instruments and heterojunction IP cores,and the IEEE 1500 standard is used for the accessing of memory IP core test.The SOC test scheduling control network based on these three IEEE standards can realize the scheduling of various test data through five pins of JTAG.It has the advantages of using less PAD resources,simple structure,easy operation,easy inheritance and strong scalability.This paper focuses on the following aspects of the SOC test scheduling control network:1)Introduce how the three IEEE standards work.According to the hierarchical relationship,the main functions of the six functional levels of IEEE 1149.7 are introduced in detail;the structure of the IEEE 1687 and IEEE 1500 standards and the working principle of the main functional modules are described in detail.2)According to the respective functional characteristics of the three IEEE standards,test strategy and project development,a comprehensive analysis of the requirements of the network,obtained SOC test scheduling control network architecture and module division, forming CLTAPC,DFX,HOST,SIB,LVTAP,WTAP and TAP control network,a total of 7 typical modules.3)Detailed design of the seven modules of the SOC test scheduling control network architecture,including the definition of the module interface,function descriptions,instruction and data register definitions.4)According to the function characteristics of the whole test scheduling control network,seven test points were extracted.A system level test case was built using C language to write deterministic test methods.The test case is simulated by using the VCS tool,and the execution process of the waveform is analyzed in detail.The simulation results show that the designed SOC test scheduling control network based on IEEE standard is able to schedule all kinds of test data correctly and achieve the desired effect.