UVM Based Ethernet PHY Auto-Negotiation Circuitverification Methodology Research

With the continuous development of semiconductor materials,devices,process technologies and the continuous improvement of circuit design technology,the number of transistors that can be integrated under the same area has increased dramatically,the functions that can be achieved by a single chip have become more and more powerful.Integrated circuits have already been the key technological field for research and development in various countries.Compared to developed countries,China's integrated circuit industry is relatively weak,the latest report shows that China annually imports hundreds of billions of dollars of chips from developed countries,which accounts for 95% of the total chip usage.Rapidly localize the chip and ridding of technological dependence on developed countries become more and more important than ever before.In order to achieve this goal at an early date,it is necessary to speed up the localization process of existing chips,and the bottleneck of shortening the chip development cycle is to shorten the verification cycle of the chip,and the proportion of data verification and statistical integrated circuits exceeds the whole chip.More than 70% of the development cycle,as long as the verification is correct,shortening the verification cycle as much as possible has become a key part of the project development process.The traditional verification method makes low coverage and poor reusability,and it takes a lot of time to write directional verification testcases,which can no longer meet the verification requirements in the future integrated circuit design flow.UVM verification method can significantly shorten the verification time,replace the verification engineer's work with the work of the machine,reduce the workload of the verification engineer,and have more reusability.The current UVM verification methodology has become the mainstream development direction of future verification methods.This paper combines the actual examples of the Ethernet PHY auto-negotiation module project that the author actually participated in.First of all,it studies the defects of traditional verification methods and the advantages of UVM verification methodology.Second,it studies the unique UVM phase,TLM mechanisms and the way each component works in UVM.Then it builds a corresponding UVM verification platform for the auto-negotiation module,including generating transaction-level incentives,creating various components of the verification platform,writing corresponding reference models and register models,connecting corresponding components to achieve synchronous communication between components and writing modules.Verify the specification and use NC-Sim for simulation verification.Use the automated comparison and waveform inspection methods to verify the test design.The collection function coverage rate reaches 100%.The verification results show that compared with the traditional verification method,the use of the predefined library in the UVM verification methodology can greatly shorten the development time of the verification platform.The constrained random excitation construction method reduces the development difficulty of the verification incentive,and the automated comparison.As a result,the inspection strategy improves the degree of automation of the platform.The use of the register model reduces the amount of code used to verify the use case and improves the flexibility of the verification platform.Therefore,adopting the UVM verification methodology can effectively reduce the workload of verification engineers,greatly increase the efficiency of verification,save manpower and time,and reduce the cost of verification.This is of great significance to the goal of realizing rapid chip localization and makes an important value in the project development process.