Research And Implementation On Reconfigurable Pipeling Co-processor For Bone-conduction Speech Enhancement Algorithm

The advantage of bonekocker technology is that people can hear voice without ears but skull, and this has changed the traditional conception of voice on people, especially the people who need to communicate in a noisy environment. However, the boneknocker can not only transmit voice but also transmit wind noise and grating by the skull in actual applications, which disturb the efficiency of voice transmit.This dissertation focuses on the research of Reconfigurable Pipelining co-processor of bonekocker speech enhancement So C. The main contributions of this dissertation are as follow.1. This Paper analyzes the DFD(data flow diagram)and CFG(control flow graph) of speech enhancement algorithm on single-channel bonekocker equipment. The circulation flow pattern, arithmetic operation type and data dependency were extracted through DFG and CFG for speech enhancement algorithm of bonekocker, and provide a basic for reconfigurable pipelining's application customization of So C and reconfigurable compiling.2. The architecture scheme of reconfigurable So C for bonekocker speech enhancement processing algorithms is designed. The co-processor's architecture of reconfigurable So C is ACRP(Application C ustomization Reconfigurable Pipelining), reconfigurable switching network using a small overhead reconfigurable multiplexer switching network. According to analyze and abstract the frequent instruction template, an application Customization Processing Element(CPE) is designed to support the frequent instruction sequence efficiently. The main structural and functional parameters are selectable configuration.3. Reconfigurable pipeline have featares of data path and functio nal components reconfigurable, high flexibility, reconfigurable overhead small, support multiple data stream characteristics, this can significantly improve the efficiency of data- intensive computing model. In order to meet the needs of reconfigurable pipelined data flow, we designed a Multi- functional register file(MFRF).The MFRF combine the characteristics of general register file with the functions of heap and stack. The experimental results show that MFRF can effectively support a variety of data-streams for reconfigurable pipeline, the results of simulation matrix multiplication and FFT, compared with the general register file, Matrix multiplication with a significant performance improvement.4. We build a RTL simulation system with reconfigurable pipelining co-processor using Verilog HDL on the expe riment environment of software emulation with Quartus II. We implemented the hardware synthesis and simulate analysis on the EP3C55F484 FPGA chip of reconfigurable pipelining co-processor. Then run the reconfigurable pipelining co-processor with FPGA hardware model for FFT matrix multiplication a first-order smoothing algorithms. The experimental results show that performance of reconfigurable pipelining co-processor with FPGA hardware model is wel.